1 / 32

Sequential Circuits

Complex tasks cannot be done (efficiently) with combinational circuits Most digital systems are sequential circuits Block diagram of sequential circuit:. Sequential Circuits. FEEDBACK (loop). Storage element is a place holder used to remember something

paul-bennett
Télécharger la présentation

Sequential Circuits

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Complex tasks cannot be done (efficiently) with combinational circuits Most digital systems are sequential circuits Block diagram of sequential circuit: Sequential Circuits FEEDBACK (loop) Storage element isa place holderused to remember something That something is calledthe state. ' present ' and ' next ' refer to anordering Ed F. Deprettere Digital Design Leiden University

  2. Place holder order 1 2 . . n n+1 . . X(n) X(n+1) Place holder releases current state and stores next state Current state at n+1 = next state at n place holders are built from FLIP-FLOPS which are built from latches Ed F. Deprettere Digital Design Leiden University

  3. There is a gate delay (propagation delay, tpd) Example:buffer Do we need new gates? No, we don’tif we add Time to BehavioryieldingTimed Logic. A gate is built from physical transistors:it is causal ! i.e., output can not appear before or simultaneously with the input. (t) (t+tpd) X X Is logically possible, not physically: out istpdtime units laterthan in: in at time t , out at time t + tpd Ed F. Deprettere Digital Design Leiden University

  4. Asynchronous and synchronous SCs Asynchronous:signals are defined at all timesTime is continuous Synchronous:signals at specific time instantsTime is discrete. Designing asynchronous sequential circuits is more difficult, yet not always avoidable ( sometimes even preferable) Flip-flopsare storage elements in synchronous circuits, but arethemselves constructed from asynchronous blocks calledLatches. The simplest latch is built from the buffer: 1/2tpd 1/2 tpd tpd Ed F. Deprettere Digital Design Leiden University

  5. X(t) X(t+tpd) 1/2tpd tpd time (t) tpd tpd tpd Open & renew input Close & remove input Close t tpd What if I close the switch? Be carefull : tpd depends on technology! Ed F. Deprettere Digital Design Leiden University

  6. States of flip-flops(memory elements) are set by clockpulses (no pulse, no state change even if input changes) All flip-flops are set at the same time (synchronous operation) Clocked Sequential Circuits Synchronous circuits that usea clockto synchronize. Time instances are at fixed distances.(! Synchronous ismore general than clocked!) Ed F. Deprettere Digital Design Leiden University

  7. Q is a name ! SR latch R S Q Q Q S Q R 2 3 4 1 SR Latch — Normal Operation The latched buffer is not very useful:information can not be changed. Replace the buffer’s inverter components by NORs or NANDs 1 active RESET 2 hold RESET 3 active SET 4 hold SET Ed F. Deprettere Digital Design Leiden University

  8. Many flip-flops (latches) have two outputs Typical names are Q and Qbar Under most (normal) conditions, Qbar = Q', Q = Qbar'. When Q = 1 (Qbar = 0) the flip-flop is in the set state (the flip-flop is set) When Q = 0 (Qbar = 1) the flip-flop is in the resetstate The behavior of a flip-flop (latch) can be described with a function table (similar to truth table) Function table for SR latch Comments Ed F. Deprettere Digital Design Leiden University

  9. SR latch SR latch is NOR basedSR latch is NAND based Q S Q R S (set) Q Normal state is 00 (SR) or 11 (SR) S=1 : go to set state. Before going back to reset, make S=0 to avoid undefined state. Q R (reset) S R Q Q S R Q Q • 0 1 0 • 0 0 1 0 • 0 1 0 1 • 0 0 0 1 • 1 1 0 0 Set state 0 1 1 0 1 1 1 0 1 0 0 1 1 1 0 1 0 0 0 0 Set state Reset state Reset state S =0 Undefined Undefined SR Latch Diagrams and function tables Ed F. Deprettere Digital Design Leiden University

  10. SR latch with control input Getting better control on the latch SR latch Diagram Function Table Ed F. Deprettere Digital Design Leiden University

  11. C   Q D TG   Q  TG  A good latch has well defined states and simple driving conditions The D Latch is such one. It’s behavior is very simple: Ed F. Deprettere Digital Design Leiden University

  12. Block diagram The D Latch Is a real good latch: 1 control input, 1 data input well defined states Function Table D latch Ed F. Deprettere Digital Design Leiden University

  13. A[k] sequent nextcurrentstate Flip-Flops The D latch can be used as aplace holderbut not in afeedback loop Why? Simple place holder take C=1 to get Q=A[k] then C=0 to hold. Feedback loop You want to read out the current and write in the next state at the same time instant:output (current state) must not see input (next state)as is the case with the D latch. Flip-flops are what we need. Ed F. Deprettere Digital Design Leiden University

  14. Q P S S1 S2 C C1 C2 Q P R R1 R2 Is a symbol, Not an inverter SR Master-Slave Flip-Flop Great?! Remember:SR latch may get into undefined state(oscillation danger) Master Latch Slave Latch Look at symbols Analysis: C = 0 —> C1 = 0, Current state Q not affected (remembered by M) —> C2 = 1, S copies current state Q to output P C = 1 —> C1 = 1, M reads next state (from S,R) —> C2 = 0, output of S not affected ( current state , P, remembered) Ed F. Deprettere Digital Design Leiden University

  15. C S R Q P SR Master-Slave Flip-Flop (cont’d) Time behavior: read pages 251/252 Be aware: response is assumed to be correct when clock goes to 0. Ed F. Deprettere Digital Design Leiden University

  16. C S R Q P Actual CC has also delay! If S input of flip-flop is not stable when clock goes high, then situation below may occur! FF can respond to input values that occur anytime during clock pulse. (therefore: MS flip-flop also called pulse-triggered FF) (1) (2) At (1), Q=0; at (2) S and R both zero, so Q should stay 0 (See function table). Output P=1 is wrong. SR Master-Slave Flip-Flop (cont’d) Wrong: Ed F. Deprettere Digital Design Leiden University

  17. Q P D D S2 C1 C2 C Q P R2 Q P D D S2 C C1 C2 Q P R2 D Flip-flop Is likewise a MS Flip-Flop but has no pulse-triggered behavior because it has not a hold-state (see function table) Therefore: it is called edge-triggered. Here Negative edge-triggered (because it is the C-transition 1-to-0 that causes P to change). A Positive edge-triggered D Flip-Flop has an additional inverter at C-input. Ed F. Deprettere Digital Design Leiden University

  18. D Q C T If Q(t)=0, then Q(t+1) = D(t) = T(t) If Q(t)=1, then Q(t+1) = D(t) = T(t) Or, if T=0, then Q(t+1) = Q(t), else Q(t+1) = Q(t) Toggle Flip-Flop Ed F. Deprettere Digital Design Leiden University

  19. Latches Positive control Negative control MS FF's Positive clock Negative clock Edge FF's 0-1 clock 1-0 clock Symbols and relations C(ontrol) is positive (negative) if it is active at logic 1 (0). Clock is positive or 'high' (negative or 'low') if no circle (if circle) appears at the C input. Ed F. Deprettere Digital Design Leiden University

  20. Characteristic Tables Characteristic Table SR positive edge triggered flip-flop Triggered means clock control Table is same for negative edge triggered FF. In that case add circle external to C. Ed F. Deprettere Digital Design Leiden University

  21. Characteristic Table D C Positive edge triggered D flip-flop Characteristic Table Positive edge triggered T flip-flop D and T Flip-flops Ed F. Deprettere Digital Design Leiden University

  22. S R C D Q Q 0 1 X X 1 0 1 0 X X 0 1 0 0 X X undefined 1 1 0 0 1 1 1 0 1 0 IEEE standard notation  S Q 1D C1 R  Cn controls all nX inputs, Hence NOT S and R. Circle: S is active at logic 0. (apply 0 to activate) Direct, asynchronous inputs In combinational circuits, we used enable bits to distinguish between operate and don’t operate. In sequential circuits, we use asynchronous S(et) and/or R(eset) Inputs to initialize states. Ed F. Deprettere Digital Design Leiden University

  23. Inputs Outputs Combinational circuit Flip-flops Clock pulses How to analyse sequential circuits Obviously more complicated than combinatorial circuits Two parts : combinational : no problem flip-flop part FF inputs depend on CC outputsbeing feedforward functions of CC inputs. FF outputs depend onFF inputs and Clock Hence on CC inputs and Clock. Ed F. Deprettere Digital Design Leiden University

  24. A X D C B D clock C Y Be Systematic Inputs : X Outputs : Y State Variables : A, B Input Equations DA = AX+BX DB = A'X Output Equations Y = (A+B)X' Ed F. Deprettere Digital Design Leiden University

  25. Inputs : X Outputs : Y States Variables : A, B Input Equations DA = AX+BX DB = A'X Output Equations Y = (A+B)X' State Table State Table Ed F. Deprettere Digital Design Leiden University

  26. Characteristic Table TFlip-Flop Example: a counter Input equations T0 = 1, T1 = Q0, T2 = Q0Q1 Ed F. Deprettere Digital Design Leiden University

  27. Is another way of writing state table Inputs : X Outputs : Y States Variables : A, B Input Equations DA = AX+BX DB = A'X Output Equations Y = (A+B)X' Two-Dimensional State Table 2D State Table Time trace Ed F. Deprettere Digital Design Leiden University

  28. Present Next State Output Z State X = 0 X = 1 X = 0 X = 1 A A B 0 0 B A C 0 0 C D C 0 0 D A B 0 1 0/0 1/0 1/0 1/0 0/0 A B C D 0/0 1/1 0/0 Design State Table In general we code m states with n bits, There are 4 states which we code with 2 bits each A = 00 B = 01 C = 11 ! D = 10 Ed F. Deprettere Digital Design Leiden University

  29. Present State Next State Output Z Q1 Q0 X = 0 X = 1 X = 0 X = 1 A 0 0 0 0 0 1 0 0 B 0 1 0 0 1 1 0 0 C 1 1 1 0 1 1 0 0 D 1 0 0 0 0 1 0 1 Input eqs. Output Q1(t+1) = D1(Q1, Q0, X) = Σ(3,6,7) = Q1.Q0 + Q0.X Q0(t+1) = D0(Q1, Q0, X) = Σ(1,3,5,6) = X Z(Q1, Q0, X) = Σm(5) = Q1.Q0’.X Q0X Q1 Q1 Q0 00 01 11 10 0 1 X Design (cont’d) Why is A = 00? Circuit? Always in this order, and without omitting any of the symbols, please. Ed F. Deprettere Digital Design Leiden University

  30. [ ] = Z [ ] = X [ ] = Y Other example X is a (long) sequence of bits [….. b(n), b(n-1), ….., b(n-x), b(n-x-1), …….. b(1), b(0)] = X Y is a sequence of zeros and ones. [….. 0 0 …………1 0 ………….. 0 0 ] = Y X is the concatenation of a set of words, least significant bit fist (to the right, that is) and ending when the corresponding y-bit is 1; y-bits are zero otherwise. A circuit is to be designed that obtains the two’s complement of the words in X in a serial manner. Z is the sequence of two’s complements. A z-bit corresponding to a x-bit Must appear during the same clock cycle the x-bit is presented at the input. Ed F. Deprettere Digital Design Leiden University

  31. X Y 1 0 1 0 0 0 → 0 1 0 1 1 1 + 0 0 0 0 1 = 1 1 0 0 0 0 0 0 0 0 0 carry to be ‘remembered’ 0 0 1 1 1 0 1 0 1 1 1 1 0 1 1 0 0 0 → carry is state 10/1 XY/Z 00/1 00/0 1 10/0 0 X * 0 * 0 * 1 * 1 Y 0 1 0 1 0 1 0 1 C 1 0 1 1 1 0 1 1 X’ 1 1 0 0 Z 1 0 0 1 Other example (cont’d) Recall: two’s complement = one’s complement + ‘1’ *1/* ‘1’ *1/* Last bit of word First bit of next word Ed F. Deprettere Digital Design Leiden University

  32. Y Present state Inputs Next State Output Q(t) X Y Q(t+1) Z X’ T Z 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 Q D C RESET XY Q Q X 00 01 11 10 0 1 Y One major problem: power-on resets FF making initial state 0 which is not o.k. Why? Other example (cont’d) State table HALF ADDER Q(t+1) = D(Q(t),X,Y) = Σm(1,3,4,5,7) = Y + QX’ Z(Q(t), X,Y) = Σm(0,1,6,7) = XOR(X’,Q) Ed F. Deprettere Digital Design Leiden University

More Related