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Synthesis of synchronous elastic architectures

Synthesis of synchronous elastic architectures

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Synthesis of synchronous elastic architectures

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  1. Synthesis of synchronouselastic architectures Jordi Cortadella (Universitat Politècnica Catalunya) Mike Kishinevsky (Intel Corp.) Bill Grundmann (Intel Corp.)

  2. Network of Computing Units Out In B3 B1 B2

  3. Network of Computing Units Out In B3 B1 B2

  4. Network of Computing Units Out In B3 B1 B2

  5. Latency-insensitive (elastic) system Out In B3 B1 B2 Every block onlymakes one step when all inputs are valid

  6. Why • Scalable • Modular (Plug & Play) • Tolerance to variable latency • Communication • Computation • Not asynchronous • Use existing design paradigms • CAD tools

  7. Outline • The cost of elasticity • SELF: an elastic protocol • Basic implementation (linear pipelines) • General netlists (forks and joins) • Formal models and verification • Synthesis of elastic architectures • Related work

  8. Area, power and latency Gated clock Control Valid Valid Stop Stop CLK What’s the cost ofelasticity? Elastic block Core Data Data

  9. Communication channel sender receiver Data Data Long wires: slow transmission

  10. Data Pipelined communication sender receiver Data

  11. Data Pipelined communication sender receiver Data

  12. Data Pipelined communication sender receiver Data How about if the sender does not always send valid data?

  13. The Valid bit sender receiver Data Data Valid Valid

  14. Data Valid The Valid bit sender receiver Data Valid

  15. Data Valid The Valid bit sender receiver Data Valid

  16. Data Valid The Valid bit sender receiver Data Valid

  17. Data Valid The Valid bit sender receiver Data Valid How about if the receiver is not always ready ?

  18. sender receiver Data Data Valid Valid Stop Stop 0 0 0 0 0 The Stop bit

  19. sender receiver Data Data Valid Valid Stop Stop 0 0 0 1 1 The Stop bit

  20. sender receiver Data Data Valid Valid Stop Stop 0 0 1 1 1 The Stop bit

  21. sender receiver Data Data Valid Valid Stop Stop 1 1 1 1 1 The Stop bit Back-pressure

  22. sender receiver Data Data Valid Valid Stop Stop 0 0 0 0 1 The Stop bit Long combinational path

  23. sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)

  24. sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)

  25. sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)

  26. sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)

  27. sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)

  28. sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)

  29. sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)

  30. sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)

  31. sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage) • Handshakes with short wires • Double storage required

  32. Proposal: an elastic protocol • SELF (Synchronous ELastic Flow) • Simple and provably correct • Data-path with no overhead in: • Area • Latency • Energy • Negligible control overhead • Fine-grain elasticity

  33. Flip-flops vs. latches sender receiver FF FF 1 cycle

  34. Flip-flops vs. latches sender receiver H L H L 1 cycle

  35. Flip-flops vs. latches sender receiver H L H L 1 cycle

  36. Flip-flops vs. latches sender receiver H L H L 1 cycle

  37. Flip-flops vs. latches sender receiver H L H L 1 cycle

  38. Flip-flops vs. latches sender receiver H L H L 1 cycle

  39. Flip-flops vs. latches sender receiver H L H L 1 cycle

  40. Flip-flops vs. latches sender receiver H L H L 1 cycle Flip-flops already have a double storage capability, but …

  41. Flip-flops vs. latches sender receiver H L H L 1 cycle Not allowed in conventional FF-based design !

  42. H L H L Flip-flops vs. latches sender receiver 1 cycle Let’s make the master/slave latches independent

  43. H L H L Flip-flops vs. latches sender receiver ½ cycle ½ cycle Let’s make the master/slave latches independent Only half of the latches (H or L) can move tokens

  44. Elastic buffer keeps datawhile stop is in flight Cannot be done withSingle Edge Flops without double pumping Use latches inside MS W1R1 W2R1 W1R2 Carloni’s relay station belongs to this class W2R2

  45. SELF (linear communication) sender receiver Data Data En En En En V V V V Valid Valid 1 1 1 1 Stop Stop S S S S

  46. SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S

  47. SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S

  48. SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S

  49. SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S

  50. SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S