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Session 1: FPGA Hardware Synthesis - Synchronous Finite State Machines

Session 1: FPGA Hardware Synthesis - Synchronous Finite State Machines. Sri Venkateswara College of Engineering and Technology, Chittor, India, August 30 th 2013. Bharathwaj “Bart” Muthuswamy muthuswamy@msoe.edu Assistant Professor of Electrical Engineering

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Session 1: FPGA Hardware Synthesis - Synchronous Finite State Machines

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  1. Session 1: FPGA Hardware Synthesis -Synchronous Finite State Machines Sri Venkateswara College of Engineering and Technology, Chittor, India, August 30th 2013 Bharathwaj “Bart” Muthuswamy muthuswamy@msoe.edu Assistant Professor of Electrical Engineering Milwaukee School of Engineering (MSOE) BS (2002), MS (2005), PhD (2009) from Cal (University of California, Berkeley) Advisor: Dr. Leon O Chua, co-advisor: Dr. Pravin Varaiya http://www.harpgroup.org/muthuswamy Slides (.pdf) can be found online: http://www.harpgroup.org/muthuswamy/talks/August30th2013-TimingClosureFPGAWorkshop-SVCET/

  2. Outline I. FPGA Hardware Synthesis II. The concept of a finite state machine III. Moore Machine Example IV. Mealy Machine Example V. Conclusions VI. References

  3. FPGA Hardware Synthesis Figure 1. Steps involved in synthesizing a design onto an FPGA [1]

  4. Outline I. FPGA Hardware Synthesis II. The concept of a finite state machine III. Moore Machine Example IV. Mealy Machine Example V. Conclusions VI. References

  5. The Concept of a Finite State Machine Figure 2. Generic Block Diagram for a Finite State Machine [2] Let us also briefly talk about the hardware platform that we are going to use…

  6. Outline I. FPGA Hardware Synthesis II. The concept of a finite state machine III. Moore Machine Example IV. Mealy Machine Example V. Conclusions VI. References

  7. Moore Machine Example : Problem Statement Design a twenty-four hour clock using Moore Machines.

  8. Outline I. FPGA Hardware Synthesis II. The concept of a finite state machine III. Moore Machine Example IV. Mealy Machine Example V. Conclusions VI. References

  9. Mealy Machine Example : Problem Statement Design a Mealy Level-To-Pulse converter [3].

  10. Conclusion In the next session, we are going to timing close our design…

  11. References • Altera Design Flow For Xilinx Users. http://www.altera.com/literature/an/an307.pdf Available, Online. Last accessed August 8th 2013. • Muthuswamy, B. and Banerjee, S. “A Route to Chaos Using Integrated Circuits: The FPGA Approach”. To be published by Springer in October 2013. • MIT OCW Finite State Machines Handout. http://web.mit.edu/6.111/www/f2012/handouts/L05.pdf Available, Online. Last accessed August 8th 2013.

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