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Analysis and Synthesis of Synchronous Sequential Circuits

Analysis and Synthesis of Synchronous Sequential Circuits. A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the circuit When no clock – the circuit is asynchronous:. Analysis and Synthesis of Synchronous Sequential Circuits.

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Analysis and Synthesis of Synchronous Sequential Circuits

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  1. Analysis and Synthesis of Synchronous Sequential Circuits • A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the circuit • When noclock – thecircuit is asynchronous:

  2. Analysis and Synthesis of Synchronous Sequential Circuits • The “state” of a synchronous sequential circuit: • All the FF/memory element outputs • Can change only upon clock transition (pulse/edge) • Two models for synchronous sequential circuits: • Mealy model • Outputs are a function of state and inputs • Moore model • Outputs are a function of state only

  3. Mealy model • Next state (Y1,…,Yr) achieved on clock transition

  4. Mealy model • Input (x1,…,xn), output (z1,…,zm), present state (y1,…,yr) and next state (Y1,…,Yr) are where gi and hi are Boolean functions, or in vector form

  5. Moore model x1 xn Combinational logic Y1 Yr Memory y1 yr clock Combinational logic z1 zm

  6. Mealy machine example • State diagram and state table • Assumes  transitions Problem?

  7. Moore machine example • State diagram and state table • Output is f(state) only • Inputs – no effect

  8. Mealy vs. Moore • Representations can be transformed into each other • Advantages and disadvantages Mealy Moore - glitches + no glitches - problem sampling + easier to design + lesser total # states

  9. Analysis precedes synthesis • Analysis of logic diagrams of sequential circuits • Inputs, state variables, outputs, logic equations ? • Mealy or Moore type?

  10. Analysis • Input sequence: x = 01101000

  11. Analysis • Deriving state diagram and state table • Given circuit diagram  Boolean equations • Notation: yk represents y(k t) • k = integer; t = clock period • May assign numbers to states: 0  state A; 1  state B

  12. Analysis • Deriving state table from K-maps Map for Yk=yk+1 Map for zk

  13. Analysis example • Synchronous sequential circuit with flip-flops • Negative edge-triggered • Inputs? • States? • Outputs? • Logic equations?

  14. Analysis example • Timing diagram

  15. Analysis example • State table and K-maps

  16. Analysis example • Combining the K-maps into state table

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