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Sequential Circuits’ Analysis

Sequential Circuits’ Analysis. Sequential Circuit Analysis. Standard Graphics Symbols Characteristic Tables Characteristic/Input Equations State Tables State Diagrams Analysis using JK flip-flops. S. R. SR-latch. Standard Graphics Symbols. Latches. S. D. D. R. C. C. S’R’-latch.

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Sequential Circuits’ Analysis

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  1. Sequential Circuits’ Analysis

  2. Sequential Circuit Analysis • Standard Graphics Symbols • Characteristic Tables • Characteristic/Input Equations • State Tables • State Diagrams • Analysis using JK flip-flops asep@stmik-raharja.com

  3. S R SR-latch Standard Graphics Symbols Latches S D D R C C S’R’-latch D-latch with C=1 D-latch with C=0 asep@stmik-raharja.com

  4. Standard Graphics Symbols (cont.) Master-Slave Flip Flops J S J S C C C C K R K R Triggered JK Triggered SR Triggered JK Triggered SR asep@stmik-raharja.com

  5. Standard Graphics Symbols (cont.) Edge-triggered Flip Flops J D J D C C K C K C Triggered JK Triggered D Triggered JK Triggered D Rising Edge Falling Edge Rising Edge Falling Edge asep@stmik-raharja.com

  6. Characteristic Tables • Defines the logical properties of a flip-flop (such as a truth table does for a logic gate). • Q(t) – present state at time t • Q(t+1) – next state at time t+1 asep@stmik-raharja.com

  7. Characteristic Tables (cont.) asep@stmik-raharja.com

  8. Characteristic Tables (cont.) asep@stmik-raharja.com

  9. Characteristic Tables (cont.) Characteristic Equation: Q(t+1) = D(t) asep@stmik-raharja.com

  10. Characteristic Tables (cont.) Obtained by JK Flip-Flop with J=K=T Characteristic Equation: Q(t+1) = T’Q(t) + TQ(t)’ asep@stmik-raharja.com

  11. Asynchronous Set/Reset • Many times it is desirable to asynchronously (i.e., independent of the clock) set or reset FFs. • Example: At power-up so that we can start from a known state. • Asynchronous set == direct set == Preset • Asynchronous reset == direct reset == Clear asep@stmik-raharja.com

  12. S 1J C1 1K R Asynchronous Set/Reset (cont.) Cn indicates that Cn controls all other inputs whose label starts with n. In this case, C1 controls J1 and K1. Independent of CLK Independent of CLK Function Table IEEE standard graphics symbol for JK-FF with direct set & reset asep@stmik-raharja.com

  13. Sequential Circuit Analysis • Analysis: Consists of obtaining a suitable description that demonstrates the time sequence of inputs, outputs, and states. • Logic diagram: Boolean gates, flip-flops (of any kind), and appropriate interconnections. • The logic diagram is derived from any of the following: • Boolean Equations (FF-Inputs, Outputs) • State Table • State Diagram asep@stmik-raharja.com

  14. Flip-Flop Input Equations • An algebraic representation used to specify the logic driving the inputs of the FFs. • They imply the type of FFs to be used and fully specify the combinational logic that drives the FFs inputs. asep@stmik-raharja.com

  15. Example: Implementing FF Input Equations • Consider JA = XB+Y’C and KA = YB’+C • J, K imply the type of the FF (in this case, a JK-FF). • The index (A) denotes the output of the FF. Observe that the triggering type is not specified by the FF input eqs. You are either given this explicitly, or you have to assume it.For this case, we assume a positive edge-triggered clocking scheme. A JA J C A’ KA K asep@stmik-raharja.com

  16. Example: Implementing FF Input Equations X B JA A J Y C C KA A’ K Clock • JA = XB+Y’C • KA = YB’+C asep@stmik-raharja.com

  17. Fully specified logic diagrams • Do FF input equations fully specify a sequential circuit? No! • We also need the primary output boolean equations. List of boolean equationsfor the primary outputs. Comb. Circuit List of FF input equations. FFs asep@stmik-raharja.com

  18. Example • FF input equations: • DA = AX + BX • DB = A’X • Primary output boolean equations: • Y = (A + B)X’ •  # FFs: 2, FF-type: D •  # inputs: 1 (X), # outputs: 1 (Y) •  Logic diagram … (see Figure 4.18, pp. 203) asep@stmik-raharja.com

  19. State Table • Enumerates the relationship between inputs, outputs, and states of the sequential circuit. • Given a circuit with n inputs and m flip-flops, the corresponding state table contains 2n+m rows. asep@stmik-raharja.com

  20. State Table (cont.) DA = AX + BX = A(t+1) DB = A’X = B(t+1) Y = (A + B)X’ State Table asep@stmik-raharja.com

  21. State Table – Alternative Representation State Table asep@stmik-raharja.com

  22. Mealy Vs Moore machines • Mealy model: • Both outputs and next state depend both on primary inputs AND present state. • Moore model: • Only next state depends directly on primary inputs AND present state. Outputs depend only on present state. asep@stmik-raharja.com

  23. Canonical Sequential Circuit Combinational Network s(t+1) s(t) State Register next state present state x(t) present inputs clock output z(t) asep@stmik-raharja.com

  24. Mealy Machine C1 C2 s(t+1) State Register next state s(t) z(t) present state x(t) present inputs clock asep@stmik-raharja.com

  25. Moore Machine C2 C1 z(t) s(t+1) State Register next state s(t) present state x(t) present inputs clock asep@stmik-raharja.com

  26. X DA A D Z Y C clock Example of a Moore machine • Obtain the logic diagram and state table for: • DA = A  X Y • Z = A asep@stmik-raharja.com

  27. Example of a Moore machine (cont.) State Table Alternative State Table X DA A Z D Y C clock asep@stmik-raharja.com

  28. State Tables for JK flip-flops • Two step procedure: • Obtain binary values of each FF input equation in terms of present state and input variables. • Use corresponding FF characteristic table to determine the next state. asep@stmik-raharja.com

  29. Example • JA = B, KA = BX’ • JB = X’, KB = AX’ + A’X = A  X •  2 JK-FFs needed: JK-FF Characteristic Table JA JB J J B A C C KA A’ B’ KB K K asep@stmik-raharja.com

  30. Example (cont.) Step 1: Use FF input equations asep@stmik-raharja.com

  31. Example (cont.) Step 2:Use FF inputs and JK characteristic table asep@stmik-raharja.com

  32. State Diagrams • Graphical representation of a state table. • Graph node with label s denotes state s • Graph edge with label X denotes transition between two states when input X is applied S X asep@stmik-raharja.com

  33. Example: Mealy model State Table Possible states = { 00, 01, 10, 11 }  4 nodes in state diagram asep@stmik-raharja.com

  34. 0/0 1/0 01 00 0/1 0/1 0/1 1/0 10 1/0 11 1/0 Example: Mealy model (cont.) State Diagram I/O S1 S2 Reads as:When at state s1 and apply input I, we get output O and proceed to state s2. asep@stmik-raharja.com

  35. Example: Moore model State Table Possible states = { 0, 1 }  2 nodes in state diagram asep@stmik-raharja.com

  36. 00,11 01,10 0/0 1/1 01,10 00,11 Example: Moore model (cont.) State Diagram I S1/O1 S2/O2 Reads as:When at state s1 with output O1 and apply input I, we proceed to state s2 with Output O2. asep@stmik-raharja.com

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