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AXI Interfacing IP Creation

ECE 699: Lecture 5. AXI Interfacing IP Creation. Required Reading. The ZYNQ Book Tutorials. Tutorial 4: IP Creation Exercise 4A: Creating IP in HDL. The ZYNQ Book. Chapter 19: AXI Interfacing. ARM AMBA AXI Protocol v1.0: Specification. Chapter 1: Introduction

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AXI Interfacing IP Creation

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  1. ECE 699: Lecture 5 AXI Interfacing IP Creation

  2. Required Reading The ZYNQ Book Tutorials • Tutorial 4: IP Creation • Exercise 4A: Creating IP in HDL The ZYNQ Book • Chapter 19: AXI Interfacing ARM AMBA AXI Protocol v1.0: Specification • Chapter 1: Introduction • Chapter 2: Signal Descriptions • Chapter 3: Channel Handshake • Chapter 4: Addressing Options • Chapter 9: Data Buses

  3. Recommended Reading P. Schaumont, A Practical Introduction to Hardware/Software Codesign, 2nd Ed. • Chapter 10: On-Chip Buses M.S. Sadri, ZYNQ Training (presentations and videos) • Lesson 1 : What is AXI? • Lesson 2 : What is an AXI Interconnect? • Lesson 3 : AXI Stream Interface

  4. Components of Today’s Systems-on-Chip Source: M.S. Sadri, Zynq Training

  5. Connectivity Requirements Source: M.S. Sadri, Zynq Training

  6. SoC Buses Source: M.S. Sadri, Zynq Training

  7. Solution Adopted in ZYNQ Advanced Microcontroller Bus Architecture (AMBA): an open-standard, on-chip interconnect specification for the connection and management of functional blocks in system-on-a-chip (SoC) designs. First version introduced by ARM in 1996. AMBA Advanced eXtensible Interface 4 (AXI4): the fourth generation of AMBA interface defined in the AMBA 4 specification, targeted at high performance, high clock frequency systems. Introduced by ARM in 2010. Source: M.S. Sadri, Zynq Training

  8. Basic Concepts Source: M.S. Sadri, Zynq Training

  9. Communication BetweenAXI Master and AXI Slave Source: M.S. Sadri, Zynq Training

  10. Additional Information Exchanged BetweenAXI Master and AXI Slave Source: M.S. Sadri, Zynq Training

  11. Five Channels of AXI Interface Source: M.S. Sadri, Zynq Training

  12. Connecting Masters and Slaves Source: M.S. Sadri, Zynq Training

  13. AXI Interconnect

  14. Interconnect vs. Interface

  15. Addressing of Slaves Source: M.S. Sadri, Zynq Training

  16. AXI Interconnect Address Decoding Source: M.S. Sadri, Zynq Training

  17. Clock Domain and Width Conversion Source: M.S. Sadri, Zynq Training

  18. Hierarchical AXI Interconnects Source: M.S. Sadri, Zynq Training

  19. Simple Address Definition Rules No Overlaps Source: M.S. Sadri, Zynq Training

  20. Simple Address Definition Rules Address Alignment

  21. Point-to-Point Data Flows Source: M.S. Sadri, Zynq Training

  22. AXI Memory-Mapped vs. AXI Stream Source: M.S. Sadri, Zynq Training

  23. Selected AXI Stream Ports Source: M.S. Sadri, Zynq Training

  24. AXI Port Naming Conventions Source: M.S. Sadri, Zynq Training

  25. AXI Interfaces (High-Performance) (Shared Bus) (Peripheral) (Point-to-Point Bus) Source: M.S. Sadri, Zynq Training

  26. Concept of a Burst Source: M.S. Sadri, Zynq Training

  27. Competing System-on-Chip Bus Standards AMBA: Advanced Microcontroller Bus Architecture AXI: Advanced eXtensible Interface AHB: AMBA High-speed Bus APB: AMBA Peripheral Bus PLB: Processor Local Bus OPB: On-chip Peripheral Bus MM: Memory Mapped ST: Streaming Source: A Practical Introduction to Hardware/Software Codesign

  28. AXI4 Write Source: The Zynq Book

  29. AXI4 Read Source: The Zynq Book

  30. AXI4 Interface Write Address Channel Write Data Channel Write Response Channel Read Address Channel Read Data Channel Source: The Zynq Book

  31. Prefixes of Ports from Particular Channels Source: The Zynq Book

  32. Timing Diagram Conventions Source: ARM AMBA AXI Protocol v1.0: Specification

  33. VALID before READY Handshake Source: ARM AMBA AXI Protocol v1.0: Specification

  34. READY before VALID Handshake Source: ARM AMBA AXI Protocol v1.0: Specification

  35. VALID with READY Handshake Source: ARM AMBA AXI Protocol v1.0: Specification

  36. Channel Architecture of Reads Source: ARM AMBA AXI Protocol v1.0: Specification

  37. Read Burst Source: ARM AMBA AXI Protocol v1.0: Specification

  38. Overlapping Read Bursts Source: ARM AMBA AXI Protocol v1.0: Specification

  39. Read Transaction Handshake Dependencies

  40. Channel Architecture of Writes

  41. Write Burst Source: ARM AMBA AXI Protocol v1.0: Specification

  42. Write Transaction Handshake Dependencies Source: ARM AMBA AXI Protocol v1.0: Specification

  43. Source: ARM AMBA AXI Protocol v1.0: Specification

  44. Role of Write Strobe WSTRB WSTRB[n] corresponds to WDATA[8*n+7 downto 8*n] Source: ARM AMBA AXI Protocol v1.0: Specification

  45. Narrow Transfer Example with 8-bit Transfers Source: ARM AMBA AXI Protocol v1.0: Specification

  46. Narrow Transfer Example with 32-bit Transfers Source: ARM AMBA AXI Protocol v1.0: Specification

  47. Aligned and Unaligned Word Transfers on a 32-bit Bus Source: ARM AMBA AXI Protocol v1.0: Specification

  48. Aligned and Unaligned Word Transfers on a 64-bit Bus Source: ARM AMBA AXI Protocol v1.0: Specification

  49. Example of IP Core with AXI Interface Source: The Zynq Book

  50. Exit from Reset Source: ARM AMBA AXI Protocol v1.0: Specification

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