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Designing State Machines

Designing State Machines. Discussion D8.5 Section 13.9. Sequence Detectors. Mealy and Moore Machines A Sequence Detector using D Flip-flops Verilog Program. clr. Combinational Network. s(t+1). s(t). State Register. next state. present state. x(t). present input. present

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Designing State Machines

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  1. Designing State Machines Discussion D8.5 Section 13.9

  2. Sequence Detectors • Mealy and Moore Machines • A Sequence Detector using D Flip-flops • Verilog Program

  3. clr Combinational Network s(t+1) s(t) State Register next state present state x(t) present input present output clk z(t) Canonical Sequential Network

  4. clr C1 C2 s(t+1) State Register next state s(t) z(t) present state x(t) present input clk Mealy Machine

  5. clr C2 C1 z(t) s(t+1) State Register next state s(t) present state x(t) present input clk Moore Machine

  6. VerilogCanonical Sequential Network clr Combinational Network s(t+1) s(t) State Register next state present state x(t) present input present output clk z(t) always @(present_state or x) always @(posedge clk or posedge clr)

  7. VerilogMealy Machine always @(present_state or x) clr C1 C2 s(t+1) State Register next state s(t) z(t) present state x(t) present input always @(present_state or x) clk always @(posedge clk or posedge clr)

  8. VerilogMoore Machine clr C2 C1 z(t) s(t+1) State Register next state s(t) present state x(t) present input always @(present_state or x) always @(present_state or x) clk always @(posedge clk or posedge clr)

  9. Sequence Detectors • Mealy and Moore Machines • A Sequence Detector using D Flip-flops • Verilog Program

  10. ExampleDetect input sequence 1101 fsm din clk dout clr din dout 1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0

  11. 0 1 1 0 0 1 CLR 0 1 0 1 Creating a State DiagramDetect input sequence 1101 S1 0 S0 0 S11 0 S1101 1 S110 0

  12. Sequence Detectors • Mealy and Moore Machines • A Sequence Detector using D Flip-flops • Verilog Program

  13. seqdet.v seqdet din clk dout clr // Sequence detector -- Detect 1101 module seqdet(clk, clr, din, dout); input clk, clr, din; output dout; reg dout;

  14. clr dout din seqdet.v reg[2:0] present_state, next_state; parameter S0 = 3'b000, S1 =3'b001, S11 = 3'b010, S110 = 3'b011, S1101 = 3'b100;

  15. seqdet.v clr dout din always @(posedge clk or posedge clr) begin if (clr == 1) present_state <= S0; else present_state <= next_state; end

  16. seqdet.v S1 0 0 1 1 S0 0 0 S11 0 0 CLR 1 0 1 0 S1101 1 S110 0 1 // C1: Next State always @(present_state or din) begin case(present_state) S0: if(din == 1) next_state <= S1; else next_state <= S0; S1: if(din == 1) next_state <= S11; else next_state <= S0; S11: if(din == 0) next_state <= S110; else next_state <= S11; S110: if(din == 1) next_state <= S1101; else next_state <= S0; S1101: if(din == 0) next_state <= S0; else next_state <= S11; default next_state <= S0; endcase end

  17. seqdet.v clr dout din // C2: Outputs always @(present_state) begin if(present_state == S1101) dout <=1; else dout <= 0; end endmodule

  18. Detect input sequence 1101

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