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MICROPROCESSORS AND APPLICATIONS

MICROPROCESSORS AND APPLICATIONS. Mr. DEEPAK P. Associate Professor ECE Department SNGCE. UNIT 4. 19/9/14. DEEPAK.P. Programmable Interface devices. 3. 19/9/14. DEEPAK.P. Programmable Peripheral Interface [8255]. 4. PPI 8255.

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MICROPROCESSORS AND APPLICATIONS

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  1. MICROPROCESSORS AND APPLICATIONS Mr. DEEPAK P. Associate Professor ECE Department SNGCE DEEPAK.P

  2. UNIT 4 DEEPAK.P

  3. 19/9/14 DEEPAK.P Programmable Interface devices 3

  4. 19/9/14 DEEPAK.P Programmable Peripheral Interface [8255] 4

  5. PPI 8255 • It is an I/O port chip used for interfacing I/O devices with microprocessor. • The parallel input-output port chip 8255 is also called as programmable peripheral input-output port. • The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit microprocessors.

  6. PPI 8255 • It has 24 input/output lines which may be individually programmed in groups. • The groups of I/O pins are named as Group A , Group B and group C upper and Group C lower. • Each of these two groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four lines or a 4-bit port.

  7. PPI 8255 • The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. • All of these ports can function independently either as input or as output ports. • This can be achieved by programming the bits of an internal register of 8255 called as control word register ( CWR ).

  8. Signals of 8255

  9. Block Diagram of 8255

  10. Block Diagram of 8255 • Two control groups, labeled group A control and group B control define how the three I/O ports operate. • One of the 4 bit group is associated with group A control and the other 4 bit group with group B control device signals. • The upper 4 bits of port C are associated with group A control while the lower 4 bits are associated with group B control. • The final logic blocks are read/write control logic and data bus buffer.

  11. Block Diagram of 8255 • These blocks provide the electrical interface between the micro processor and 8255. • The data bus buffer buffers the data I/O lines to/from the microprocessor data bus. • The read/write control logic routes the data to and from the correct internal registers with the right timing.

  12. Pin Diagram of 8255

  13. Pin Diagram of 8255 • The 8255 is a 40 pin integrated circuit (IC), designed to perform a variety of interface functions in a computer environment. • D0 - D7 These are the data input/output lines for the device. • All information read from and written to the 8255 occurs via these 8 data lines. • CS (Chip Select Input). If this line is a logical 0, the microprocessor can read and write to the 8255. • RD (Read Input) Whenever this input line is a logical 0 and the CS input is a logical 0, the 8255 data outputs are enabled onto the system data bus.

  14. Pin Diagram of 8255 • WR (Write Input) Whenever this input line is a logical 0 and the CS input is a logical 0, data is written to the 8255 from the system data bus • A0 - A1 (Address Inputs) The logical combination of these two input lines determines which internal register of the 8255 data is written to or read from. • RESET The 8255 is placed into its reset state if this input line is a logical 1. All peripheral ports are set to the input mode.

  15. Pin Diagram of 8255 • PA0 - PA7, PB0 - PB7, PC0 - PC7 These signal lines are used as 8-bit I/O ports. • They can be connected to peripheral devices. • The 8255 has three 8 bit I/O ports and each one can be connected to the physical lines of an external device. • These lines are labeled PA0-PA7, PB0-PB7, and PC0-PC7. • The groups of the signals are divided into three different I/O ports labeled port A (PA), port B (PB), and port C (PC).

  16. Pin Diagram of 8255

  17. Control word Format of 8255

  18. Modes of 8255 • There are two basic modes of operation of 8255, They are: • 1. I/O mode. • 2. BSR mode. • In I/O mode, the 8255 ports work as programmable I/O ports, while • In BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits.

  19. Modes of 8255 • There are 3 I/O modes of operation for the ports of 8255. • Mode 0, Mode 1, and Mode 2 • 1) Mode 0 - Basic I/O mode • 2) Mode 1 - Strobed I/O mode • 3) Mode 2 - Strobed bi-directional I/O

  20. Modes of 8255 • Mode 0 Operation • It is Basic or Simple I/O. • It does not use any handshake signals. • It is used for interfacing an i/p device or an o/p device. • It is used when timing characteristics of I/O devices is well known

  21. Modes of 8255 • Mode 1 Operation • It uses handshake I/O. • 3 lines are used for handshaking. • It is used for interfacing an i/p device or an o/p device. • Mode 1 operation is used when timing characteristics of I/O devices is not well known, or used when I/O devices supply or receive data at irregular intervals.

  22. Modes of 8255 • Handshake signals of the port inform the processor that the data is available, data transfer complete etc. • Mode 2 Operation • It is bi-directional handshake I/O. • Mode 2 operation uses 5 lines for handshaking. • It is used with an I/O device that receives data some times and sends data sometimes. • Mode 2 operation is useful when timing characteristics of I/O devices is not well known, or when I/O devices supply or receive data at irregular intervals.

  23. Modes of 8255 • Port A, Port B and Port C can work in Mode 0 • Port A and Port B can work in Mode 1 • Only Port A can work in Mode 2

  24. 25/9/14 DEEPAK.P Programmable Interrupt Controller [8259] 24

  25. Programmable Interrupt Controller • The 8085 has only 5 interrupt line. • If I/O devices need more interrupt line to transfer data, we go for Programmable Interrupt controllers. • The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for the Intel 8085 and Intel 8086 microprocessors.

  26. Programmable Interrupt Controller • In computing, a programmable interrupt controller (PIC) is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs.

  27. Programmable Interrupt Controller 8259 • PICs typically have a common set of registers: • Interrupt Request Register (IRR), • In-Service Register (ISR), • Interrupt Mask Register (IMR). • The IRR sores the interrupts request that is coming from 8 interrupt lines • The ISR register stores all the interrupts that are currently being serviced • The IMR stores the masking bits ie which interrupts are to be ignored and not acknowledged.

  28. Block Diagram of PIC 8259

  29. Block Diagram of PIC 8259 • There are three registers, an Interrupt Mask Register (IMR), an Interrupt Request Register (IRR), and an In-Service Register (ISR). • Data bus buffer and read-write logic: are used to configure the internal registers of the chip. • Interrupt mast register (IMR): is used to enable or mask out the individual interrupt inputs through bits M0 to M7. 0= enable, 1= masked out. • Interrupt request register (IRR): is used to indicate all interrupt levels requesting service.

  30. Block Diagram of PIC 8259 • In service register (ISR): is used to store all interrupt levels which are currently being serviced. • Priority resolver: This block determines the priorities of the bits set in the IRR. • The highest priority is selected and strobed into the corresponding bit of the ISR during the INTA sequence. • Cascade-buffer comparator: Sends the address of the selected chip to the slaves in the master mode and decodes the status indicated by the master to find own address to respond.

  31. Block Diagram of PIC 8259 • One or more of the INTERRUPT REQUEST lines (IR0 - IR7) are raised high, setting the corresponding IRR bit(s). • The 82C59A evaluates those requests in the priority resolver and sends an interrupt (INT) to the CPU, if appropriate. • The CPU acknowledges the lNT and responds with an INTA pulse. • The 82C59 does not drive the data bus during the first INTA pulse.

  32. Block Diagram of PIC 8259 • During this INTA pulse, the appropriate ISR bit is set and the corresponding bit in the IRR is reset. • This completes the interrupt cycle. • In the AEOI mode, the ISR bit is reset at the end of the second INTA pulse. • Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine.

  33. Pin Diagram of PIC 8259

  34. Signals of PIC 8259

  35. Signals of PIC 8259 • Eight interrupt input request lines named IRQ0 through IRQ7, • An interrupt request output line named INTR, • Interrupt acknowledgment line named INTA, • D0 through D7 for communicating the interrupt level or vector offset. • Other connections include CAS0 through CAS2 for cascading between 8259s.

  36. Pin Diagram of PIC 8259

  37. Pin Diagram of PIC 8259 • The 8259 programmable interrupt controller (PIC) adds eight vectored priority encoded interrupts to the microprocessor. • This controller can be expanded without additional hardware to accept up to 64 interrupt requests. • This requires a master 8259 and eight 8259 slaves. • 8259s are cascaded by connecting the INT line of one slave 8259 to the IRQ line of one master 8259.

  38. Pin Diagram of PIC 8259 • SP/EN

  39. Connecting Multiple Devices to Processors

  40. Connecting Multiple Devices to Processors

  41. Command Words of 8259 • The command words of 8259A are classified in two groups • Initialization command words (ICW) and • Operation command words (OCW) • Initialization Command Words (ICW): • Before it starts functioning, the 8259 must be initialized by writing two to four command words into the respective command word registers. • These are called as initialized command words

  42. Command Words of 8259

  43. Command Words of 8259

  44. Command Words of 8259

  45. Command Words of 8259

  46. Command Words of 8259

  47. Command Words of 8259

  48. Modes of 8259

  49. Modes of 8259

  50. Modes of 8259

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