Computer Architecture I: Digital Design Dr. Robert D. Kent

1. Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Sequential Circuits Part I

2. Review • We have studied logic design in the contexts of Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD). • We have studied the design of a number of specific, practical functional circuits with a view to re-using those circuits as components in MSI design. Adders Subtractors Comparator Decoders Multiplexers • We note the differing design approaches, or emphases, effected by differential layering of abstraction. (The same design issue arises in the context of software engineering as well.) SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components

3. Goals • Previously, we studied Combinational circuits, or networks. • These are time independent because the inputs, once provided, immediately establish what the outputs will be.

4. Goals • Previously, we studied Combinational circuits, or networks. • These are time independent because the inputs, once provided, immediately establish what the outputs will be. • We now continue to consider Sequential Networks • These are time dependent in that the initial values of the circuit outputs are used to provide input to the same circuit.

5. Goals • Previously, we studied Combinational circuits, or networks. • These are time independent because the inputs, once provided, immediately establish what the outputs will be. • We now continue to consider Sequential Networks • These are time dependent in that the initial values of the circuit outputs are used to provide input to the same circuit. • This is called feedback.

6. Goals • The properties of sequential networks yield the capability to design memory circuits • characterized by internal states and secondary states that describe the behaviour and values in a circuit before and after inputs are applied.

7. Goals • The properties of sequential networks yield the capability to design memory circuits • characterized by internal states and secondary states that describe the behaviour and values in a circuit before and after inputs are applied. • There are two kinds of sequential networks

8. Goals • The properties of sequential networks yield the capability to design memory circuits • characterized by internal states and secondary states that describe the behaviour and values in a circuit before and after inputs are applied. • There are two kinds of sequential networks • Synchronous - behaviour is governed by the inputs only during specific discrete time intervals

9. Goals • The properties of sequential networks yield the capability to design memory circuits • characterized by internal states and secondary states that describe the behaviour and values in a circuit before and after inputs are applied. • There are two kinds of sequential networks • Synchronous - behaviour is governed by the inputs only during specific discrete time intervals • Asynchronous - behaviour is governed by the inputs immediately as they are applied

10. Goals • The basic logic element is called the Flip-Flop circuit.

11. Goals • The basic logic element is called the Flip-Flop circuit. • We will study first a primitive element - the basic bi-stable element.

12. Goals • The basic logic element is called the Flip-Flop circuit. • We will study first a primitive element - the basic bi-stable element. • ... then study Latches.

13. Goals • The basic logic element is called the Flip-Flop circuit. • We will study first a primitive element - the basic bi-stable element. • ... then study Latches. • ... then proceed to Flip-Flops and Gated Latches/Flip-Flops.

14. Goals • The basic logic element is called the Flip-Flop circuit. • We will study first a primitive element - the basic bi-stable element. • ... then study Latches. • ... then proceed to Flip-Flops and Gated Latches/Flip-Flops. • Finally, we will establish an MSI based model of a register and discuss how to construct load, read, shift and count capabilities into the register designs.

15. Basic Bi-stable Element • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs.

16. Basic Bi-stable Element X X’ Y Y’ Q Q’ • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs. • This circuit has the representation:

17. Basic Bi-stable Element X X’ Y Y’ Q Q’ • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs. • This circuit has the representation:Trace: Starting from the top gate 1. If X = 0 then Q = X’ = 1

18. Basic Bi-stable Element X X’ Y Y’ Q Q’ • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs. • This circuit has the representation:Trace: Starting from the top gate 1. If X = 0 then Q = X’ = 1 2. Thus, Y = X’ = Q = 1 implies Q’ = Y’ = 0

19. Basic Bi-stable Element X X’ Y Y’ Q Q’ • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs. • This circuit has the representation:Trace: Starting from the top gate 1. If X = 0 then Q = X’ = 1 2. Thus, Y = X’ = Q = 1 implies Q’ = Y’ = 0This is self-consistent, since X = Y’ = Q’.

20. Basic Bi-stable Element X X’ Y Y’ Q Q’ • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs. • This circuit has the representation:Trace: Starting from the top gate 1. If X = 0 then Q = X’ = 1 2. Thus, Y = X’ = Q = 1 implies Q’ = Y’ = 0This is self-consistent, since X = Y’ = Q’. The same self-consistency applies when X = 1 (Y = 0).Therefore, we say the state is stable.

21. Basic Bi-stable Element X X’ Y Y’ Q Q’ • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs. • This circuit has the representation: • The term bi-stable implies that there are two possible states Q = 0 , Q’ = 1 and Q = 1 , Q’ = 0

22. Basic Bi-stable Element X X’ Y Y’ Q Q’ • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs. • This circuit has the representation: • The term bi-stable implies that there are two possible statesQ = 0 , Q’ = 1 and Q = 1 , Q’ = 0 • There is a third state that is technically possible, called the meta-stable state. This applies when the voltage signal values of X and Y (hence, Q and Q’) are precisely half way between their HI and LO values; however, these in-between states are typically short lived. Q Transition Voltage Smooth Signal Profile Transition Voltage Q’

23. Basic Bi-stable Element X X’ Y Y’ Q Q’ • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs. • This circuit has the representation: • The term bi-stable implies that there are two possible states Q = 0 , Q’ = 1 and Q = 1 , Q’ = 0 • There is a third state that is technically possible, called the meta-stable state. This applies when the voltage signal values of X and Y (hence, Q and Q’) are precisely half way between their HI and LO values; however, these in-between states are typically short lived. Q Transition Voltage Noisy Signal Profile Transition Voltage Q’

24. Basic Bi-stable Element X X’ Y Y’ Q Q’ • The basic bi-stable element is a simple device characterized by • no inputs !!! • Two outputs. • This circuit has the representation: • Although the bi-stable element is worth studying for its simple properties, it is relatively useless as a computer circuit because • its value cannot be changed from the “outside” - once power is applied its value is set (after a brief time period to achieve stability) and does not change henceforth.

25. Latches

26. Latches • A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state.

27. Latches • A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state. • Set the state - store a value 1 in the circuit; also called pre-setting the state.

28. Latches • A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state. • Set the state - store a value 1 in the circuit; also called pre-setting the state. • Reset the state - store a value 0 in the circuit; also called clearing the state.

29. Latches • A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state. • Set the state - store a value 1 in the circuit; also called pre-setting the state. • Reset the state - store a value 0 in the circuit; also called clearing the state. • We will consider next a class of flip-flops called Latches.

30. Latches • A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state. • Set the state - store a value 1 in the circuit; also called pre-setting the state. • Reset the state - store a value 0 in the circuit; also called clearing the state. • We will consider next a class of flip-flops called Latches. • Characterized by the fact that the timing of the output changes is not controlled (except possibly by an Enable, or Clock, signal).

31. SR Latch

32. SR Latch RS QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’

33. SR Latch RS QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’

34. SR Latch RQ0’ Q0S QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’ Q0 and Q0’ are the output signal values when the S and R inputs are applied - they are also applied as inputs to the nor gates.

35. SR Latch RS QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’ Once the nor gates have stabilized the outputs, Q1 and Q1’ are then fed back as inputs.

36. SR Latch RS QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’ The nor gates must stabilize to a final output , Q2 and Q2’.

37. SR Latch 00 QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 00 1 01 10

38. SR Latch 00 QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 00 10 1 01 10

39. SR Latch 00 QQ’ Stable! • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 00 10 10 1 01 10

40. SR Latch 00 QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 01 0 10 01

41. SR Latch 00 QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 01 01 0 10 01

42. SR Latch 00 QQ’ Stable! • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 01 01 01 0 10 01

43. SR Latch 10 QQ’ Stable! • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 0 1 0 1 0 1 0 0 10 10 1 0 1 0 > 01 > 1 10

44. SR Latch 10 QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 0 1 0 1 0 1 0 0 1 0 1 0 1 0 10 11 0 10 01

45. SR Latch 10 QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 0 1 0 1 0 1 0 0 1 0 1 0 1 0 10 11 00 0 1 > 00 > 0 0 > 01 > 0

46. SR Latch 10 QQ’ Stable! • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 0 1 0 1 0 1 0 0 1 0 1 0 1 0 10 11 00 00 1 * 1 > 0 > 00 > 0 > 1 0 > 01 > 0

47. SR Latch 01 QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 0 1 0 1 0 1 0 0 1 0 1 0 1 0 10 1 1 0 0 0 0 1 *1 00 1 01 10

48. SR Latch 01 QQ’ • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 0 1 0 1 0 1 0 0 1 0 1 0 1 0 10 1 1 0 0 0 0 1 *1 00 10 0 0 > 01 > 0 1 > 00 > 0

49. SR Latch 01 QQ’ Stable! • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 0 1 0 1 0 1 0 0 1 0 1 0 1 0 10 1 1 0 0 0 0 1 *1 00 10 01 0 * 0 > 0 > 11 > 0 > 0 1 > 00 > 0

50. SR Latch 01 QQ’ Stable! • This circuit consists of two cross-coupled nor gates with • two inputs, S and R, referred to as set and reset inputs • two outputs, Q and Q’ • Truth table:S R Q0 Q0’ Q1 Q1’ Q2 Q2’0 0 0 1 0 1 0 10 0 1 0 1 0 1 0 0 1 0 1 0 1 0 10 1 1 0 0 0 0 1 *1 0 0 1 0 0 1 0 *1 01 01 0 1 0 1 > 10 > 0 0 > 01 > 1