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I/O system

I/O system. High-level subsystems. I/O System. Low-level subsystems. Application. File System. Virtual memory Management. I/O System Interface. Block device interface. Open/close Read/write. Stream device interface. Open/close get/put io_control. Network interface.

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I/O system

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  1. I/O system

  2. High-level subsystems I/O System Low-level subsystems Application File System Virtual memory Management I/O System Interface Block device interface Open/close Read/write Stream device interface Open/close get/put io_control Network interface Open/close read/write send/receive Block-oriented device management Stream-oriented device management Network communication software Device independent software … … … Device dependant software CD-ROW Driver Hard disk drive Keyboard driver Printer driver Network driver SW/HW interface … … … CD-ROW controller Hard disk controller Keyboard controller Printer controller Network controller HW controls devices ::::::::::

  3. Device Controller Interface Controller Driver Describes the operation which the driver wants the controller to carry out opcode register write operand registers Indicates if controller is busy and that it cannot accept any new requests (boolean value) Device Indicates a ‘completed operation’ report to the driver busy register read status register data buffer read/write Transfers data to and from the device

  4. Explicit Device Interface Memory-mapped Interfaces Extension of Main Memory opcode register operand registers opcode register opcode register opcode register operand registers operand registers operand registers vs. 0 0 Main Memory Main Memory n -1 n -1 Controllers dev_0 dev_0 dev_1 dev_1 dev_n dev_n 2 different types of instructions used to address Main Memory and Device Same format of instructions used to address Main Memory and Device

  5. Programmed Input/Output with polling opcode register operand registers 2 1 busy register 4 status register 5 data buffer 3 6 6 1 CPU writes operands required for input in operand registers 2 CPU writes opcode for input operation; controller executes; flag set to busy 3 Data transferred from device to data buffer 4 During data transfer in 3, CPU polls controller by testing busy flag 5 After operation completes CPU checks status register for problems 6 If no errors found, CPU transfers data from data buffer to Main Memory Controller Device busy CPU Main Memory

  6. Programmed Input/Output with Interrupts 2 1 4 5 3 6 6 1 CPU writes operands required for input in operand registers 2 CPU writes opcode for input operation; controller executes; flag set to busy 3 Data transferred from device to data buffer 4 Operation complete, controller issues interrupt; running pr. suspends & waiting pr. resumes 5 Resumed processchecks status register for problems 6 If no errors found, processtransfers data from data buffer to Main Memory Controller opcode register operand registers ControlLogic Device busy register busy CPU status register data buffer Main Memory

  7. Direct Memory Access I/O (DMA) opcode register 2 operand registers 1 busy register 5 status register 6 data buffer 3 4 1 CPU writes operands required for input in operand registers 2 CPU writes opcode for input operation; controller executes; flag set to busy 3 Data transferred from device to data buffer 4 Controller copies data between main memory and data buffer; (repeated) 5 After operation completes, controller resets busy flag to 0 and sends interrupt to CPU 6 CPU reads status register to check for successful operation CPU overhead is high in fast devices. DMA reduces the CPU overhead in initiating and monitoring individual data transfer between device and main memory. Controller ControlLogic Device busy CPU Main Memory

  8. DMA – CPU Cycle Stealing DMA CPU Memory Device CPU CTL 1

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