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Driver Waveform Computation for Timing Analysis with Multiple Voltage Threshold Driver Models

Driver Waveform Computation for Timing Analysis with Multiple Voltage Threshold Driver Models. Peter Feldmann*, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta IBM T.J. Watson Research, Yorktown Heights, NY*

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Driver Waveform Computation for Timing Analysis with Multiple Voltage Threshold Driver Models

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  1. Driver Waveform Computation for Timing Analysis with Multiple Voltage Threshold Driver Models Peter Feldmann*, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta IBM T.J. Watson Research, Yorktown Heights, NY* IBM Systems & Technology Group, Hopewell Junction, NY June 11, 2008 DAC 2008, Anaheim, CA

  2. Introduction • Traditional gate delay characterization • Capacitive loads only • Output signal assumed to be a ramp • Delays and slews functions of input slew and capacitive load • Sources of inaccuracy • Non-ramp-like waveforms • Highly resistive modern day interconnects • Inductive effects

  3. Concept of effective capacitance (Ceff) • Ideally match output waveform using Ceff instead of RC load • Match charge in interval [tv=0 , tv=0.5Vdd] • Single number – not accurate enough RC Line 1.0 0.8 A 0.6 Current / Voltage at A 0.4 A 0.2 0.0 Ceff 0 25 50 75 100 125 150 Time (ps)

  4. Op Voltage v1 v2 v3 v4 v5 v6 Time t1 t2 t3 t4 t5 t6 dotLib + ECSM Op Voltage Waveform Table InSlew CLoad Recent industry trends • Non-linear current source models (CSM) • Effective Current Source Model (ECSM) • Cadence, Magma • Driving current I = fI(V, Cdyn) • For given input slew, characterization data stored as: Time = T(V, C) PWL* *PWL = Piece Wise Linear

  5. Io I2 Output Current I3 I1 PWL I4 I5 I6 t1 t2 t3 t4 t5 t6 t0 dotLib + CCS Op Current Waveform Table InSlew CLoad Time Recent industry trends (contd.) • Non-linear current source models • Composite Current Source (CCS) • Synopsys • Driving current I = fI(V, Cdyn) • For given input slew, characterization data stored as: I = FI(T, C)

  6. Simulating current source models • For a given input ramp (slew) • Transformations required (T ~ time) • T = T(V, C)  I = fI(V, C) • I = FI(T, C)  I = fI(V, C) • Approximation, accuracy loss • Accurate transformation requires • High degree of continuity • Smoothness

  7. Contributions • Accurate and efficient analytical framework for driver waveform computation • Novel algorithm for simulation of CSM • Simulation along V axis and not T axis • Avoids time domain integration (requires smooth data, time step control etc.) • Requires model in MVTM* form: T= T(V, C) • Same as industry standard characterized data • No transformation to I = fI(V, C) • Eliminates approximations • Assumes monotonic piecewise linear output voltage waveform *Multiple Voltage Threshold Model

  8. Dynamic capacitance concept (Cdyn) • A driver’s time varying instantaneous equivalent load capacitance • Generalization for multiple voltage threshold model i(t) v(t) RC Line Time

  9. Driver waveform computation • Assume current state Tp, Vp • Goal: Given Vp+1, calculate Tp+1 • Charge supplied by driver • Assuming change in V linear for Tp Output Voltage Time unknown Tp

  10. Driver waveform computation (contd.) • Charge flowing into load in Tp: Qp • Can be expressed analytically as f(Tp+1) • Equate charge • Unknowns: Tp+1, Cd,p • Use information from driver model (characterization table) RC Line EQ1 EQ2

  11. Small testcase setup • Test common gates (INV, BUFF, AND, XOR) driving RC interconnect loads • Compare near-end waveforms • SPICE • Traditional Ceff approach • Proposed approach denoted as MVTM (Multi voltage threshold model) • Ramp of 20ps slew at gate input • Krylov method used to compute interconnect delay

  12. RC Line m 100 m R Cn Cf Results Delay and slew values are in psecs

  13. Small testcase results (contd.) In this experiment, the CMOS gate under test is a NAND2. The Cn=20fF, Cf=480fF, Rp=500. This experiment shows that MVTM follow SPICE while the Ceff technique incurs about 20% error in gate delay and about 40% in slew calculation.

  14. Large testcase setup and results • Tested on large microprocessor units • 65 nm designs • Design, runtime and memory stats +20% +5%

  15. Large testcase results (contd.) • Timing comparison with traditional Ceff based gate delay calculation • Largest difference paths analyzed in SPICE • Observed MTVM models more accurate • Within 3% of SPICE

  16. Summary • Accurate and efficient timing analysis • Based on Multiple Voltage Threshold Models • Realistic load models can be handled • Novel algorithm for simulation of CSMs • Eliminates need of intermediate transformation of models to I = fI(V, C) • Compatible with industry standards • Acceptable runtime • Limitations, assumptions • Driver input voltage waveform ramp • Monotonic output voltage waveform

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