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presenter chen kuan tsai advisor dr chun yao wang date 2012 06 15 n.
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Static Timing Analysis for Threshold Logic Circuits

Static Timing Analysis for Threshold Logic Circuits

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Static Timing Analysis for Threshold Logic Circuits

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  1. Presenter:Chen-Kuan Tsai Advisor:Dr. Chun-Yao Wang Date:2012/06/15 Static Timing Analysis for Threshold Logic Circuits

  2. Outline • Introduction • Static Timing Analysis (STA) • Threshold Logic • A Motivational Example • Problem Formulation • STA for Threshold Logic Circuits • Sensitization Criterion for Threshold Logic • Types of Threshold Logic Gates (LTGs) • Sensitization conditions • Threshold Logic-based STA • Preprocess • Path Enumeration • Path Sensitization • Experimental Result • Conclusion

  3. Introduction • Static Timing Analysis (STA) is built on top of conservative delay modeling of gates and interconnects valid under all input patterns. • Compared to timing simulation, STA can completely verify the timing of a design in a linear runtime with respect to the size of the circuit.

  4. Static Timing Analysis • Critical Path Problem • Longest path problem • Naive • Structural Analysis • May overestimate the delay • False path problem • Functional Analysis • Apply sensitization criterion to determine path sensitizability • Identify the longest sensitizable path • The accuracy depends on the sensitization criterion

  5. An Example of False Path A0 The longest path delay:6(actual delay:5) 3 3 A1 0 1 0 1 … F B0 2 2 B1 … Select : 0 1

  6. Terminologies • A path is said to be sensitized when it allows a signal transition to propagate along it. • A logic value at any input of the gate independently determines the output of the gate, called controlling value. • On the other hand, the complementary logic value of controlling value is called non-controlling value.

  7. Terminologies • A input of a gate along the path is defined as an on-input of the path, and other inputs to the gate are defined as side-inputs. • Arrival time and Required timeare used to verify timing requirements in the presence of constraints. Arrival time is the time elapsed for a signal to arrive at a certain point. Required timeis the latest time at which a signal can arrive without being longer than desired.

  8. Sensitization Criteria in Boolean Logic • Static sensitization criterion [1] • A path is static sensitizable path when all the side-inputs of the path are at non-controlling values. • May underestimate the delay, though, can be used as a lower bound to the actual delay • Exact sensitization criterion [2] • When the on-input is at a controlling value, the earlier arrived side-inputs must hold non-controlling values. • When the on-input is latest input at a non-controlling value, each of its side-input must hold a non-controlling value as well. [1] J. Benkoski, E. VandenMeersch, L.J.M. Claesen, H. De Man, “Timing Verification Using Statically Sensitizable Paths," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 10723-10784, Oct. 1990. [2]H.-C. Chen and D. H.-C. Du, “Path Sensitization in Critical Path Problem,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 196-207, Feb. 1993.

  9. Threshold Logic • A threshold function f is a multiple input function defined as shown below: y = 1 if 0if n binary inputs x1, x2, … ,xn with weights w1, w2, … ,wn a single binary output y, and a threshold value T • A threshold logic gate (LTG) is a multiple terminal device which implements a threshold function, and it can be represented as weight-threshold vector < w1, w2, … ,wn; T > • A threshold logic network is a network composed of threshold logic gates. … … … x1 x2 Xn-1 Xn w1 w2 wn-1 wn T f

  10. Features of Threshold Logic • Not every Boolean function can be realized by one threshold logic gate, for example binate Boolean functions,. • A threshold logic function must represent a unate Boolean function. But not every unate Boolean function can be synthesized as a single threshold logic gate, i.e. d. • Every Boolean function has infinitely distinct representations in the form of threshold logic. • In theory, every Boolean function can be realized as a compact threshold logic network, it can result in fewer nodes and a smaller network depth.

  11. A Motivational Example 0 0 1 0 0 0 1 1 1 X1 X2 X3 X4 X5 X6 f X1 X2 X3 X4 X5 X6 0 1 5 1 f 2 3 1 1 1 1 1 1 1 1 5 5 2 3 1 1 f 5 X1 X2 0 0 1 0 1 1 1 X3 X4 X5 X6

  12. Problem Formulation • Given a threshold logic network and its corresponding delay model with two parameters, a delay constraint D and the upper bound of critical path quantity K • Objective: • To report at most K critical paths whose path delay larger than D in a non-increasing order of delay • In this work, the threshold logic network is synthesized by an ILP-base synthesis tool [3] • For ease of analysis, we assume that the weights of every LTG are positive, and this assumption can be achieved by the negative-positive weight transformation. [3] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, “Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies,'‘ Proc. Design Automation Test in Europe, 2004, pp. 904-909.

  13. Negative-Positive Weight Transformation A B C D A E C F • Step 1: Invert the negative weights into positive weights and complement the variables with negative weights. • Step 2: Increase the threshold value by magnitude of the inverted weights. 1 3 2 1 1 1 2 -1 1 -1 f f E=B’ and F=D’

  14. Output Stability under Floating Mode • Assume the arrival order is x1 > x2 > x3 > x4 • The first condition of output stability is once the weight summation greater than or equal to the threshold value, i.e. when x4 is stabilized at 1, the LTG outputs 1. • The second condition of output stability is once the summation of stabilized-at-1s’ weights and remaining weights is less than the threshold value, i.e. when x3 is stabilized at 0, the LTG definitely outputs 0 since w2+w4<5. x1 x2 x3 x4 x1 x2 x3 x4 f f 5 5 2 2 2 1 2 2 2 1 1 0 1 X->1 0 1 X->0 X X->1 X->0

  15. Dominant Input A dominant inputxi of an LTG exists if and only if the input satisfies the following two equations either where xiis stabilized at 1 and xj is those earlier arrived input than xi and or where xi is stabilized at 0, xjis those earlier arrived input than xi, xkis those later arrived input than xi, and n is the number of inputs.

  16. Types of Threshold Logic Gates • Terminologies • A useless LTG outputs zero for all input combinations. • A critical input of an LTG exists if the LTG becomes useless after removing the inputand its corresponding weight. • A single-input group of an LTG is composed of a single input having the weight greater than or equal to the threshold value. • A multiple-input group of an LTG is composed of inputs having smaller weights than the threshold value. • An LTG having several groups is called a multiple-group LTG, otherwise, the LTG is called a single-group LTG.

  17. Input Grouping f1 • Input grouping is the process that separate s the inputs and their corresponding weight of an LTG into different groups. • For example, G1 is a single-group LTG, and both inputs X1, X2 are critical inputs to G1. G2 is a multiple-group LTG. x3 x4 x5 x6 G1 5 2 3 1 1 f 5 2 x1 x2 G2 1 1

  18. Types of Threshold Logic Gates Type-1:Multiple-group LTG, given all of its groups are single-input groups. Type-2:Single multiple-input group LTG, given all of its inputs are critical. Type-3:Single multiple-input group LTG, given one or more of its inputs are not critical. Type-4:Multiple-group LTG, given one of its groups is a multiple-input group. x1 x2 x3 x1 x2 x3 x1 x2 x3 x1 x2 x3 f f f f 1 3 3 3 1 1 1 2 1 1 1 1 1 3 1 2

  19. The Proposed Sensitization Conditions • For Type-1 and Type-2 LTGs, they can be applied the previously proposed sensitization criterion because of the identical functionality to Boolean OR/AND functions. • For Type-3 and Type-4 LTGs, the on-inputs must be the dominant inputs of the LTGs in order to be sensitized. • Furthermore, a Type-4 LTG can be decomposed as a Type-1 LTG and a Type-2/Type-3 LTG without affecting the timing computation such that the simpler sensitization criterion can be used and a smaller LTG need to be sensitized.

  20. Sensitization BDD a b c d a 0/4 wp/ wn = 0/7 4 Then-edge (1) Else-edge (0) 3 2 1 1 3/7 b b f 0/2 2/4 3/5 5/7 c c 4/5 3/4 2/3 3/4 Assume the arrival order a>b>c>d, and the on-input is c Sensitization conditions: (a, b, c, d)=(1,0,1,2) or (0,1,0,2) 1 0

  21. A dummy gate Type-4 LTG Decomposition 4 4 4 f c d e 4 2 2 2 a b gd1 a b c d e 4 4 4 2 2 2 f 4 G3:d(G3)=5 G2:d(G2)=0 • The decomposition process keeps those single-input groups and extracts the multiple-input group as a dummy gate from the original LTG such as shown above. • Next, the original LTG becomes to a Type-1 LTG and preserves those single-input groups and the threshold value. • The dummy gate preserves the original weights and threshold value, and the group is replaced by a single-input and the weight is intentionally set as the threshold value. G1:d(G1)=5

  22. A dummy gate Decomposition w/o Affecting Timing 4 4 4 f c d e 4 2 2 2 a b gd1 a b c d e 4 4 4 2 2 2 f 4 G3:d(G3)=5 G2:d(G2)=0 • Example G1:d(G1)=5 Assume Path={…, e, G1, f, …} RT(e)= RT(f) – d(G1) AT(f) = AT(e) + d(G1) RT(e)= RT(gd1) – d(G2) = RT(f) – d(G3) – d(G2) AT(f) = AT(gd1) + d(G2) = AT(e) + d(G2) + d(G3)

  23. Why Decomposition A B C • Example Assume that the on-input is B • A > B >C=> (1) A <- 0, C <- dc, B <- 1 => blocked by C (2) A <- 0, C <- dc, B <- 0=> sensitized • B > C => B <- 0, C <- dc A > B => A <- 1 => sensitized 3 3 2 1 f 1 B C 2 1 1 1 1 1 1 f A 2 D 2 3 3

  24. Why Decomposition (cont.) A B C • Example Assume that the on-input is A • B > C > A => (1) B <- 0, C <- 0, A <- 1 => sensitized (2) B <- 1, C <- 1, A <- 1 => blocked by C • D > A => D <- 0, A <- 1 => B <- 0 or C <- 0 => sensitized 3 3 2 1 f 3 B C 2 1 3 1 1 1 1 f A 1 D 1 2 2

  25. Threshold Logic-based STA • After the weight transformation and Type-4 LTG decomposition procedures, the static timing analysis is performed on a transformed threshold logic network composed of Type-1, Type-2, and Type-3 LTGs in the positive-weight form. • The gate delay model adopted in this work is a normalized delay model, 1+0.35*(the number of fanins) [4], based onthe capacitive implementation. • The wire delay is assumed to be 0 for simplicity. * Other delay configurations can be applied as well. [3]P. Celinski, S. Al-Sarawi, and D. Abbott, “Delay Analysis of Neuron-MOS and Capacitive Threshold-Logic,” Proc. Int. Conf. Electronics, Circuits and Systems, pp. 932-935, 2000.

  26. Threshold Logic-based STA (cont.) • Preprocess • Positive-Negative weight transformation • Input grouping • LTGs classification • Type-4 LTGs decomposition • Arrival time and required time computation • Violated paths enumeration • Path sensitization • Input assignment identification for satisfying the sensitization conditions of each on-input along a path • This procedure is stopped until meeting one of the following requirements • 1. The number of critical paths is enough to report. • 2. No more violated paths need to be examined.

  27. An Example 1.7 2 3 A 2 1 1 3 2 1 4 4 f1 3 1 1 1 1 3 2 E D B C 1 2.4 2.05 3 4 5 2.05 A B 2 f2 4

  28. Transformed Network 1.7 2 A 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 2.05 1 E D B C 2.4 3 4 G4 5 G1 f1 0 f 2.05 0 2 A B Sink 4 G3 Gd1

  29. Required Time Computation 1.7 A 2 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 RT:7.25 2.05 1 E D B C 2.4 3 4 G4 5 RT:8.95 G1 RT:4.5 f1 0 f 2.05 0 A B 2 Sink 4 RT:11 G3 Gd1 RT:6.9 RT:6.9

  30. Violated Path Enumeration 1.7 C-G1-G2-G4-Sink, 11.15 C-G1-G3-G4-Sink, 11.5 C-G1-G2, 9.1 A 2 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 RT:7.25 1 E D B C 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 RT:8.95 A/a: 5/1 f1 0 RT:4.5 C-G1-G3, 9.45 f 2.05 0 A B 2 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 RT:11 A/a: 4/2 RT:6.9 RT:6.9

  31. Sensitization Conditions Derivation • For Type-1 or Type-2 LTGs Case 1: • If the on-input is the earliest input, the on-input is assigned to the controlling value. Case 2: • If the on-input is the latest input, the on-input can be assigned to both values while the side-input must be assigned to the non-controlling value. Case 3: • Otherwise, the on-input must be assigned to the controlling value, and those earlier side-inputs are assigned to the non-controlling value. • For Type-3 LTGs • Construct a sensitization BDD to identify input assignments

  32. Path Sensitization 1.7 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X X 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 X X X 1 E D B C X X X X 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 X X A B 2 X X Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  33. Path Sensitization (cont.) E 1 3 4 5 0/6 1/7 4 D D 1 1 3 2 0/5 1/6 2 /7 1/6 E D B C B B B B 4/6 4/6 5/7 0/2 3/5 1/3 2/4 1/3 Sensitization candidates [1101], [1100] [0011], [0010] C C 5/5 2/2 4/4 3/3 1 0

  34. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X 1 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 X X->1 X->1 1 E D B C X->1 X->1 X->0 X->1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 X->1 X->0 A B 2 X X->0 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  35. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X 1 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 X 1 1 1 E D B C 1 1 0 1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 1->0 0 A B 2 X 0 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  36. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X 1 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 X 1 1 1 E D B C 1 1 0 1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 1 0 A B 2 X 0 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  37. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1 -> [101], [100] C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X 1 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 X 1 1 1 E D B C 1 1 0 1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 1 0 A B 2 X 0 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  38. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X 0 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 0 0 0 1 E D B C 1 1 0 0 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 0 0 A B 2 X 0 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  39. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010]-> G1 = 0 or 1-> [101], [100] C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X 0 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 0 0 0 1 E D B C 1 1 0 0 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 0 0 A B 2 X 0 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  40. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1 -> C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X 1 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 X 1 1 1 E D B C 0 0 1 1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 1 X A B 2 X 1 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  41. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1-> A = 0 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A X->0 1 2 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 X->0 1 1 1 E D B C 0 0 1 1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 1 X->0 A B 2 X->0 1 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  42. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1 -> A = 0 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 0 1 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 0 1 1 1 E D B C 0 0 1 1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 1 0 A B 2 0 1 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  43. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1-> A = 0-> [101], [100] C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 0 1 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 0 1 1 1 E D B C 0 0 1 1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 1 0 A B 2 0 1 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  44. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1 -> A = 0 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X 0 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 0 0 X 1 E D B C 0 0 1 0 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 0 X A B 2 X 1 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  45. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1 -> A = 0 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 0 0 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 0 0 0 1 E D B C 0 0 1 0 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 0 0 A B A B 2 0 1 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  46. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> G1 = 0 or 1-> A = 0-> [101], [100] C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 0 0 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 0 0 0 1 E D B C 0 0 1 0 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 0 0 A B 2 0 1 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  47. Path Sensitization (cont.) 1.7 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X X 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 X X X 1 E D B C X X X X 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 X X A B 2 X X Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  48. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> A = 1 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 X 1 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 X 1 1 1 E D B C 1 1 0 1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 1 0 A B 2 X 0 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  49. Path Sensitization (cont.) 1.7 Sensitization candidates [1101], [1100] [0011], [0010] -> A = 1 C-G1-G3-G4-Sink, 11.5 C-G1-G2-G4-Sink, 11.15 C-G1-G2, 9.1 A 2 1 1 2 0 2 1 1 0 0 1 1 f2 G2 4 1 4 3 1 1 1 1 3 2 1 1 A/a: 7.4/2 2.05 1 1 1 1 E D B C 1 1 0 1 2.4 3 4 C-G1, 7.4 G4 5 A/a: 9.45/3.4 G1 A/a: 5/1 f1 C-G1-G3, 9.45 0 f 2.05 0 1 0 A B 2 1 0 Sink 4 A/a: 11.5/4.05 G3 Gd1 A/a: 7.4/2 A/a: 4/2

  50. Path Sensitization (cont.) G1 9.1 7.4 9.45 1/5 0/4 4 G2 G2 3 1 1 0/1 4/5 1/2 3/4 G2 G1 G3 Sensitization candidates [112], [012], [002] 1 0