Lecture 11 Signal Integrity for Nanometer Design

1. Lecture 11Signal Integrity for Nanometer Design Professor Lei He EE 201A, Spring 2004 http://eda.ee.ucla.edu

2. Outline • Capacitive noise • Technology trends • Capacitance model and characteristics • Layout optimization • Inductive noise and layout optimization • When inductance become important • Inductance model and characteristics • Layout optimization • Example: SINO algorithm for both Cx and Lx noise • Other noise sources

3. Interconnect Capacitance Cx Cf Ca

4. Significance of Coupling Capacitance

5. Delay Variations Due to Coupling Capacitance Cx

6. Coupling Noise Coupling noise from two adjacent aggressors to the middle victim wire with 2x min. spacing. Rise time is 10% of project clock period. • Capacitive coupling depends strongly on both spatial and temporal relations!

7. Solution to Capacitance Computation • Accurate solution to small structure • Numerical method based on Maxwell’s equations • Raphael RC3, FastCap [Nabors-White, TCAD’91] • Efficient solution to full chip • Using tables or empirical formulas • 2.5-D capacitance model [Cong-He-Kahng-et al,DAC’97] • Capacitance is not simply A/d • A: area • d: distance

8. Cx Cx Cx Characteristics of Coupling Capacitance • Coupling capacitance virtually exists only between adjacent wires or crossing wires • Capacitance can be pre-computed for a set of (localized) interconnect structures • 2D or 2.5D capacitance model

9. Coplanar parallel interconnect structures with pre-routed Vdd and Gnd Vdd s1 s2 s3 s4 Gnd Layout to reduce impact of Cx • Noise avoidance technique: • Shield insertion • Shield is a wire directly connected to Vdd or Gnd Vdd s1 s2 G s3 s4 Gnd

10. error occurs Signal levels (V) aggressor VIH victim1 victim2 time Sampling window no error occurs Timing Sensitivity • Two nets are considered sensitive if a switching event on signal s1 happens during a sample time window for s2

11. Coplanar parallel interconnect structures with pre-routed Vdd and Gnd Vdd s1 s2 s3 s4 Gnd Layout to reduce impact of Cx • Noise avoidance techniques: • Net ordering (track assignment / net placement) Vdd s4 s1 s3 s2 Gnd

12. Spacing (nm) • Proper wire sizing and spacing may limit the impact of Cx by changing the ratio Cx/Ctotal • spacing E1 E1 Characteristics of Coupling Capacitance • Coupling capacitanceis highly sensitive to spacing

13. Relation between Delay and Noise AGG • T_max = T * ln (1/0.5-v) / ln 2 • T_min = T * ln (1/(o.5+v) / ln 2 • Typical values • V T_max/T T_min/T • 0.1 1.32 0.74 • 0.15 1.51 0.62 • 0.20 1.75 0.52 AOUT VOUT VIC VOUT w/o XTalk delay

14. Noise estimation and filtering • Rule of thumb: • Cx/C < threshold • Devgan, ICCAD’97 • V < (Rv + Rint / 2) * Cx / (1.25 Tr) • Tr: rising time for the aggressor • Vittal et al, TCAD’99 (more accurate) • V = (Rv + Rint / 2) * Cx / {0.63Tr + Ra (Ca + Cx) + Rv (Cv + Cx) + Rint * Cx} • To reduce Cx impact • Increase the driver size of victim • Decrease the driver size of aggressor • Or buffering • Need a global device size solution coupled with Time Analysis

15. Mini-Summary • Capacitive crosstalk is localized • Capacitive crosstalk affects both delay and signal integrity • Capacitive crosstalk can be minimized by • Spacing (and wire sizing) • Device sizing • Net ordering • Shielding • Buffering

16. Outline • Capacitive noise • Technology trends • Capacitance characteristics • Layout optimization • Inductive noise and layout optimization • When inductance become important • Inductance characteristics • Layout optimization • Example: SINO algorithm for both Cx and Lx noise • Other noise sources

17. Is RC Model still Sufficient? • Interconnect impedance is more than resistance • Z  R +jL •   1/tr • On-chip inductance should be considered • When L becomes comparable to R as we move towards Ghz+ designs

18. Candidates for On-Chip Inductance • Wide clock trees • Skews are different under RLC and RC models • Neighboring signals are disturbed due to large clock di/dt noise • Fast edge rate (~100ps) buses • RC model under-estimates crosstalk • P/G grids (and C4 bumps) • di/dt noise might overweight IR drop

19. VDD plane GND plane Inductance Minimization • Reference plane • wiring layers sandwiched between power planes

20. VDD shield GND shield Bus signals Inductance Minimization • Coplanar shields

21. Lx coupling between non-adjacent nets is non-trivial • Shielding is effective to reduce Lx coupling Characteristics of Coupling in 18-Bit Bus # of Shields Noise (% of Vdd) 0 (a) 0.71V (55%) 2 (b) 0.38V (29%) 5 (c) 0.17V (13%) (a) (b) (c)

22. Figure of Merit of Inductive Coupling • Inductive coupling coefficient defined as • A formula-based Keff model has been developed • High fidelity between formula and noise voltage [He-Xu, 2000]

23. Illustration of Keff Computation [XuHe,2000] Keff(i,j) = (f(i) + g(j)) / 2 f(i) = (Ni – gl)/(Nj – gl); g(j) = (gr – Nj)/(gr-Ni)

24. Mutual capacitance polarities Inductance Minimization • Staggered inverters/buffers • Differential signals • Nets with opposite switching signals can be placed adjacent to each other • Decrease Lx noise at the cost of a higher Cx noise

25. Mini-Summary • Inductive crosstalk is globalized • Inductive crosstalk affects both delay and signal integrity • Inductive crosstalk is not sensitive to • Spacing (and wire sizing) • Net ordering • Inductive crosstalk can be minimized by • Shielding • Buffering • Ground plane • Differential signal • Signal termination

26. Outline • Capacitive noise • Technology trends • Capacitance model and characteristics • Layout optimization • Inductive noise and layout optimization • When inductance become important • Inductance model and characteristics • Layout optimization • Example: SINO algorithm for both Cx and Lx noise • Other noise sources

27. Coplanar parallel interconnect structures with pre-routed Vdd and Gnd Vdd s1 s2 s3 s4 Gnd SINO Problem [He-Lepak, ISPD2K]:Simultaneous Shield Insertion and Net Ordering • Noise avoidance techniques: • Net ordering (track assignment / net placement) • Shield insertion • Shield is a wire directly connected to Vdd or Gnd Vdd s4 s1 G s3 s2 Gnd

28. SINO/NF Problem • Given: An initial placement P • Find: A new placement P’ via simultaneous shield insertion and net ordering such that: • P’ is capacitive noise free • Sensitive nets are not adjacent to each other • P’ is inductive noise free • Sensitive nets do not share a block • P’ has minimal area • Equivalent to one-shield-one-signal • When all nets are sensitive to one another

29. SINO/NB Problem • Given: An initial placement P • Find: A new placement P’ via simultaneous shield insertion and net ordering such that: • P’ is capacitive noise free • All nets in P’ have inductive noise less than a given value • P’ has minimal area

30. Properties of SINO Problems • Theorem: The optimal SINO/NF problem is NP-hard • Theorem: The optimal SINO/NB problem is NP-hard • Theorem: The maximum clique in the sensitivity graph is a lower bound on the number of blocks required for all SINO/NF solutions

31. Sensitivity Graph for SINO Problem • Graph indicating which nets are sensitive to one-another (vertices=nets, edges=nets are sensitive) One maximal clique Sensitivity graph with clique size = 3

32. Greedy Shield Insertion • Shield Insertion (SI) • Insert shield when a Cx or Lx violation occurs • Results depend strongly on the initial placement • Net Ordering + Shield Insertion (NO+SI) • First remove Cx coupling by net ordering, then perform shield insertion for Lx • Results depend weakly on the initial placement Separated NO+SI—simultaneous algorithm works better

33. Graph Coloring SINO (GC) • Our implementation: Greedy-based GC • Can solve with other GC methods as well • Main contributions of SINO-GC: • Provide lower bound measurements for SINO/NF • Comparative reference point

34. Simulated Annealing SINO (SA) • Cost Function is a weighted sum of: • Number of Cx violations • Number of Lx violations • Inductance Violation Figure (quantizes level of inductive noise) • Area of Placement • Random Moves • Combine two random blocks in placement P • Swap two (arbitrary) random s-wires in P • Move a single random s-wire in P • Insert a shield wire at a random location in P

35. Quality of SINO/NB Solutions Max. clique size in the sensitivity graph # of shields is fewer than lower bound for SINO/NF CPU time is much less than existing net ordering algorithms

36. Expand to Full-Chip Level • Shield estimation • Crosstalk Modeling (LSK model) @ chip level • Global routing synthesis • Post-routing refinement with optimal crosstalk budgeting

37. Shielding Estimation • The number of shields for min-area SINO solution is: • Linear with number of nets (Nns) • Quadratic with sensitivities (Si) • Linear with crosstalk bounds (Kth,i) • Holds for min-area SINO solutions • Estimation can be used to guide routing synthesis

38. Shielding Estimation • For known crosstalk bound (Kth,i) but unknown sensitivity rate Si and unknown number of net Nns, the number of shields is • To be used in global routing synthesis • For known Si and Nns but unknown Kth,i • To be used in noise budgeting

39. Shielding Estimation (Cont’d) • In most general case, the number of shields is

40. Computation of LSK Value Net i • For each sink, LSK value is • Sum over the path from source to sink • lj: length of the region j wherenet i is routed • Kij: sum of inductive coupling coefficients for net i in region j Region H1 Region H2 Region H3

41. Fidelity of LSK Model • For SINO solutions, higher LSK values  higher SPICE-computed noise using detailed RLC circuits

42. Converting LSK Value to Noise Voltage • Table building • Consider SINO solution of parallel interconnect buses (i.e., two-pin nets) • Compute and store both LSK values and noise voltages via SPICE simulation • Table lookup (either two-pin or multi-pin nets) • Linear interpolation and extrapolation

43. Verification of LSK Model • Errors less than 15% for SINO solutions to two-pin nets • Errors less than 20% for SINO solutions to multi-pin nets

44. GSINO Problem Formulation • Given • Pin locations of each net • RLC crosstalk bound for each sink • Decide • Rectilinear Steiner tree for each net • SINO solution within each routing region • Such that • RLC crosstalk constraint is satisfied for each sink • Wire length is minimized • Chip area is minimized

45. Overall GSINO/LD Algorithm • GSINO is NP-hard • Sub-problem SINO is NP-hard • High-quality solution via three-phase GSINO/LD algorithm • Phase I: Global routing with linear distribution of crosstalk bounds • Phase II: SINO within each region • Developed in [He-Lepak, ISPD’00] • Phase III: post-routing refinement (RF)

46. Algorithm Phase I • Routing topology generation • L and Z shape routes within bounding box of all pins • Leads to fixed path length from source to each sink • Crosstalk bound distribution • Linear distribution from source to each sink for fixed length • More sophisticated solution presented later on

47. Algorithm Phase I (Cont’d) • Routing algorithm: Iterative deletion (ID) [Cong-Preas, Integration’92] • Start with net connection graph (completed graph) • Iteratively delete the edge with the largest weight • Until graph becomes a tree α * f (wire_length) + β * density (Ri) + γ * overflow (Ri) • Density = signal nets + estimated shields (via formula) • Shielding area is reserved • Shielding area is minimized as sensitive nets are automatically distributed to different regions • Alternative global routing algorithm may be applied

48. Algorithm Phase III • Phase III: post-SINO refinement (RF) • Eliminate remaining but limited RLC noise violations • Start with most severe crosstalk-violating net • Decrease noise bound to allow one more shield in the least congested region using the formula • Until no crosstalk violations • Reduce routing congestion • Start with most congested region • Increase noise bound to remove one shield in the region using the formula • Until new SINO solution without crosstalk violation

49. Experiment Settings • Comparison among • ID+NO • ID: ID-based global routing without considering shielding in the weight function • NO: net ordering to eliminate as much capacitive coupling as possible • iSINO/LD = ID + SINO + RF (best alternative) • GSINO/LD • ITRS 0.10um technology

50. Benchmark Circuits • Large scale industrial benchmark circuits • Placement done by DRAGON [Wang et al, ICCAD’2K] • Uniform crosstalk constraints 0.15V (15% of Vdd)