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Handset applications using Low Voltage, Low Ron Switches PowerPoint Presentation
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Handset applications using Low Voltage, Low Ron Switches

Handset applications using Low Voltage, Low Ron Switches

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Handset applications using Low Voltage, Low Ron Switches

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  1. Handset applications using Low Voltage, Low Ron Switches

  2. Agenda • Product Portfolio • Handset applications • Important Specs for Handset Switches • Introduction to CMOS switches • Design Specifications • Design Tradeoffs • Analog Devices switches • Package developments • USB Switching - optional • Level Translators - optional

  3. Ron < 1 W Ron < 4 W Switches for Consumer Products1.65V – 5.5V Supply range ADG849 ADG801/2 ADG821/2/3 ADG884 3V, 5V ADG779 ADG701/2 ADG788 ADG736 ADG721/2/3 ADG819 ADG741/2 ADG888 ADG787 ADG859 Supply Range ADG841/2 ADG839 ADG836 1.65V – 3.6V 4 x SPDT 1 x SPST 1 x SPDT 2 x SPST 2 x SPDT Switch Configuration

  4. Handset Applications • Audio Switching • Speaker/ringer • Internal/external speaker – handsfree • Data Switching • USB • UART • RS232

  5. Baseband Chip 32 ohm For phone Handset Audio Switching Requirements • Configuration • eg 2 x SPDT • Board area • Tiny package • Minimum signal loss • Very low absolute Ron (~0.5ohms) • Minimum distortion • Ron Flatness • Loudness • High continuous currents 8 ohm For ring and MP3 Melody/voice & hands-free

  6. RS232 Transceiver UART Digital BB USB transceiver USB Handset Data Switching Requirements • Configuration • eg 2 x SPDT • Board area • Tiny package • Bandwidth • Eg USB 1.1 – 12Mbps • Minimum signal loss • Low absolute Ron (~2.5ohms) • Differential system-Channel matching • Delta Ron • Minimum distortion • Ron Flatness Socket Connection

  7. Important specifications in handset switches • Package • The smaller the better! • Ron • Absolute value needs to be low because the switch is in series with the Speaker • Low Ron also means lower Ron Flatness  less audio distortion • Current Handling Capabilities • P = I2R  More current through the switch means more power, thus louder audio • Power consumption • Many products are battery-operated, therefore power consumption is critical

  8. inverter driver PMOS Drain I/O Source I/O Input buffer Digital input NMOS driver Figure 1. MOS structure of a single CMOS switch channel Basic MOSFET structure of CMOS Analog switch • The CMOS switch is a parallel combination of PMOS and NMOS, Field effect transistors which operate in the non-saturated region. • The input buffer level shifts the digital input and applies signal to drivers • Drivers set the timing so that PMOS and NMOS are turned “on” or “off”. • NMOS on when gate is HI, PMOS on when gate is LO. • Basic building block for multi-channel switch

  9. Ron (Ω) Ron (Ω) Ron (Ω) Vsource (V) Vsource (V) Vsource (V) Rpmos Rnmos source drain drain source Ron of PMOS only Digital input Advantages of parallel structure • Rail-to-Rail outputs • Bi-directional operation • Relatively constant On-resistance over input signal range • For both NMOS and PMOS to have same Ron, PMOS is more than twice the area of NMOS • In parallel with Ron of NMOS only source drain Ron of CMOS

  10. Ron varies with input signal Ron varies with supply Ron varies with temperature Absolute On-Resistance

  11. Ron Flatness = Max_Ron – Min_Ron Translates directly into distortion through the switch Reduced by using back-gate switching Ron flatness/Audio Distortion Ron max Ron min

  12. Delta Ron - On resistance Channel Matching • On resistance matching (ΔRon): Difference in Ron between channels • Achieved by good layout techniques • Differential switching; ensures equal propagation delay

  13. Continuous current • Need large tracks and careful routing to handle current • Trade-off with package size • Reliability specs (current vs track width) and maximum junction temperature of silicon determine max. continuous current • Excess currents lead to electromigration over time • Reflow of metal causing increase in Ron and eventually opens • ADG849 • 400mA continuous current

  14. Charge Injection • A measure of the glitch impulse transferred from the digital input to the analog output during switching. • Caused by stray capacitance associated with the NMOS and PMOS transistors • For both NMOS and PMOS to have same Ron, PMOS is approx three times the area of NMOS hence cap of PMOS= 3x cap of NMOS • Balanced NMOS and PMOS => low Qinj • Achieved by adding compensations caps

  15. input output CS CD Capacitance • Mainly dependent on switch area • Try to minimise during layout • Ultra-Low Ron  Very large Switch Area  Lots of parasitic capacitance  Low bandwidth When switch is off When switch is on input output CS CD Cchannel • CD(off) = CD • CS(off) = CS • CS(on) = CD(on) = CS+ CD + Cchannel

  16. Leakage increase as temp increase Higher voltage => higher leakage Leakage Currents • Source : ADG836 data sheet

  17. Ron α 1/(size of switch) Continuous current needs to be high Both of these specs mean you need a large switch area This means: Larger package Higher parasitic capacitance – lower bandwidth Higher leakage Higher charge injections Design tradeoffs

  18. Specification tradeoffs • Package • Ultra-Low Ron  Very large Switch Area (package vs Ron tradeoff) • Large tracks for carrying the current  needs area • Bandwidth • Ultra-Low Ron  Very large Switch Area  Lots of parasitic capacitance  Low bandwidth • Charge injection • Large capacitance  large Charge Injection • Large Switch/track Area  no room for Qinj compensation capacitors

  19. VRANGE RON RON Flat Bandwidth Qinj Package Temp 1.8 V to 5.5 V 3 W 0.5 W 70MHz 30pC SOT66 -40°C – 85°C ADG859: 1.3W SPDT in the smallest standard package KEY BENEFITS • Package: Tiny 6-pin device in 1.65 x 1.66 x 0.57mm package • Ron: 3 W at 5V operation • Distortion: 0.5 W Specifications NEW Alternative to WLCSP

  20. VRANGE RON RON Flat Leakage Qinj Package Temp 1.8 V to 5.5 V 0.45 W 0.1 W 3nA 50pC WLCSP; LFCSP; TSSOP -40°C – 85°C ADG888 – 0.45 W Dual DPDT Switch in WLCSP/LFCSP/TSSOP KEY BENEFITS • Ultra-low RON 0.45 W typ • WLCSP and TSSOP packages • 3V, 5V operation • 400mA Continuous Current • 600mA Peak current Specifications NEW Smallest Quad Audio Sw in the world

  21. Packaging Advances LFCSP, WLCSP, advances in std plastic packages

  22. Standard package development Packaging Innovation compliments Product Innovation Standard Offerings TQFP SSOP TSOT SOIC TSSOP SOIC-N SOT SOIC-W SC70 QSOP PDIP LCC Three-pronged approach

  23. Tiny Analog Switches • Lowest Ron parts • Minimum distortion • Excellent for audio • Handset, PDA, Notebook

  24. New standard package  SOT66 Perfect for handset, PDA 35% less area than SC70 Almost half the height! Packaging Innovation compliments Product Innovation Alternative to WLCSP Avoid manuf issues! ADG3231 ADG3241 ADG859* *SPDT Audio Sw Release 2H04 Smallest 1-bit translators Smallest audio Sw

  25. SOT-666 Package Outline

  26. Wafer-Level PortfolioSmallest possible PCB footprint ADG819 SPDT 0.5 Audio ADG787 2x SPDT 4 USB1.1 ADG884 2x SPDT <1 Audio ADG888 4x SPDT 0.5 Audio Green:Released Red:Planned ADG3308 8-channel 1.2V-5.5V Translator ADG808 8x SPDT 0.5 Audio ADG3304 4-channel 1.2V-5.5V Translator

  27. Shortlist of Recommended Handset Parts

  28. USB1.1 and USB2.0 Switching ADG7xx Series, ADG8xx Series and ADG324x series

  29. USB 1.1 Switch requirements • USB 1.1 Signal levels • 3.6V max signal level, 0V min spec ADI switches are ideal for USB1.1 • All ADG7xx, most ADG8xx comply • 5V supply • Rail to rail operation • Low power (<1uA Idd) • Low Ron: • ADG7xx  ~3Ω • ADG8xx  <1Ω • Excellent flatness characteristic • ADI Advantage • Low Ron minimizes signal loss • Flat Ron reduces signal distortion

  30. USB 1.1 Switch requirements (continued) • Bandwidth > 12MHz required • USB1.1 is 12Mbps signal • Again ADG7xx ideal • Suitable configurations • Suitable bandwidth (majority >200MHz) Source: ADG736 Bandwidth 200MHz

  31. ADI guarantee compliance to the USB standard Eg.  ADG736 USB 1.1 eye diagram. • Input = random, 3V, 12Mbps differential signal • Excellent ‘open eye’ characteristic What makes a good eye diagram?

  32. New USB1.1 Compatible part: ADG787 Dual SPDT Switch(Break-Before-Make) KEY BENEFITS • Bandwidth: 150MHz • WLCSP, LFCSP & µSOIC packages • 2 W Ron • Flatness 0.4 W Specifications VRANGE RON RON Flat Bandwidth Qinj Package Temp 1.8 V to 5.5 V 2 W 0.4 W 150MHz 30pC WLCSP; LFCSP µSOIC -40°C – 85°C Schedule Released

  33. ADG787: Ron vs Supply for the 4 channels, Vdd = 4.5V Note: Channel matching very good

  34. USB 1.1 Selection Table

  35. USB 2.0 Switch requirements • USB2.0 signal levels: • +/-400mV diff signal • Bandwidth Requirements: • Random 480Mbps • Low Absolute Ron and Flatness • Similar requirements to USB1.1 • Backward Compatibility • Majority of systems need to be backward compatible with USB1.1 Source: ADG774A / ADG3257 Bandwidth: 410MHz

  36. Comparisons of eye diagrams • Input = random, 400mV, 480Mbps differential signal ADG3257 (BW = 410 MHz) ADG736 (BW = 200MHz)

  37. USB 2.0 & Universal USB Selection Table

  38. Digital Switches/Level Translators Std translators, Wide range translators, Fully bi-directional translators

  39. High +3.3 V BUS +2.5 V BUS High VOH MIN VIH MIN +3.3 V LOGIC +2.5 V LOGIC VIL MAX Low VOL MAX Low Level Translation Switch 0 V 0 V What’s driving the need for translators? • Digital voltage migration following Moore’s Law to 90nm and below • Faster operation, lower power • 90nm requires 1.2V supply • 45nm in pipeline • Expect no i/o due to COST • Analog ICs, legacy ICs at 2.5V and higher, in general • Performance reasons, S/N ratio • Need to communicate between ICs! Aim at first generation 2nd gen will be integrated “Oops parts” Translators adjust CMOS/TTL for zero bit loss

  40. ADG3241 – 3.3 V/2.5 V 1-Bit, Level Translator Digital Switch Portfolio (Low-Bit) KEY BENEFITS • Selectable Level Translation • Allow direct 3.3 V to 1.8 V translation • No need for discrete components • High Performance In Small Size • Data Rate 1.5 Gbps • Very low 225ps propagation delay • Uni-directional Level Translation, Bi-directional signal path • Tiny SC70 package

  41. ADG3245 – 3.3 V/2.5 V 8-Bit, Level TranslatorDigital Switch Portfolio (High-Bit) KEY BENEFITS • Selectable Level Translation • Allow direct 3.3 V to 1.8 V translation • No need for discrete components • High Performance In Small Size • Data Rate 1.244 Gbps • Very low 225ps propagation delay • Uni-directional Level Translation, Bi-directional signal path • TSSOP and LFCSP packages Exception is 3.3V  1.8V translation

  42. Vcc2 (1.6V) Out Vcc1 (3.6V) In1 In2 Vcc1 Vcc2 In Out EN ADG3231 ADG3232 Level Translators Key Features • Wide range voltage translation • 1.6 V to 3.6 V Supply • UP/DOWN Level Translation, Uni-Directional Signal Path • Low Current Consumption <5mA • Tiny packages: • ADG3231 in 6-SOT23 and ADG3232 in 8-SOT23 • New option… ADG3231 in SOT666 (SC89)… 40% smaller than SC70!

  43. ADG330X Family- Summary Table *Under development **Pin to pin compatible with MAX3000/1/2/3

  44. ADG3308 Bidirectional Level Translator • 8 – Channels. • Wide 1.15 to 5.5V supply range. • Low quiescent current (<5mA). • All I/O pins are tri-stated (EN=Low). • EN pin accepts only VCCY compatible levels. • Data rate >25Mbps • Packages: • 20 lead TSSOP • 20lead 4x4mm body LFCSP • 20 bump WLCSP (under development)

  45. ADG3304 Bidirectional Level Translator • 4 – Channels. • Wide 1.15 to 5.5V supply range. • Low quiescent current (<5mA). • All I/O pins are tri-stated (EN=Low). • EN pin accepts both VCCY/VCCA compatible levels. • Data rate >25Mbps • Packages: • 14 lead TSSOP • 20lead 4x4mm body LFCSP • 12 bump WLCSP (under development)

  46. ADG3301 Bidirectional Level Translator • 1 – Channel. • Wide 1.15 to 5.5V supply range. • Low quiescent current (<5mA). • All I/O pins are tri-stated (EN=Low). • EN pin accepts both VCCY/VCCA compatible levels. • Data rate >25Mbps • Packages: • 6 lead SC70

  47. ADG3300 Bidirectional Level Translator • 8 – Channels • second source for MAX3000/1/2/3. • Wide 1.15 to 5.5V supply range. • Low quiescent current (<5mA). • EN pin accepts VCCY/VCCA compatible levels. • Data rate >25Mbps • Packages: • 20 lead TSSOP • 20 bump WLCSP (under development)

  48. ADG330X Family- Applications Memory Address & Data Bus Level Translation ADG3300/8 mP Memory Data bus A I/O Y I/O Address bus A I/O Y I/O ADG3300/8

  49. ADG330X Family- Applications Level translation For Dual Full Duplex Serial Port

  50. Designing with ADG330X Level translators • General requirements for Level translators: • Supply voltage range • Speed • Driving requirements • Loading requirements