1 / 69

DISTRIBUTED COMPUTING

DISTRIBUTED COMPUTING. Sunita Mahajan , Principal, Institute of Computer Science, MET League of Colleges, Mumbai Seema Shah , Principal, Vidyalankar Institute of Technology, Mumbai University. Chapter - 7 Distributed Shared Memory. Topics. Introduction Basic concepts of DSM Hardware DSM

dianne
Télécharger la présentation

DISTRIBUTED COMPUTING

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. DISTRIBUTED COMPUTING Sunita Mahajan, Principal, Institute of Computer Science, MET League of Colleges, Mumbai Seema Shah, Principal, Vidyalankar Institute of Technology, Mumbai University

  2. Chapter - 7Distributed Shared Memory

  3. Topics • Introduction • Basic concepts of DSM • Hardware DSM • Design issues in DSM • Issues in implementing DSM systems • Heterogeneous and other DSM systems • Case Study

  4. Introduction

  5. IPC paradigms • Message passing • Shared memory • Multi computer systems are easier to build but harder to program while multiprocessor systems are complex to build but easier to program • Distributed Shared Memory systems (DSM) are both easy to program and easy to build

  6. Basic Concepts Of DSM

  7. DSM • A DSM system provides a logical abstraction of shared memory which is built using a set of interconnected nodes having physically distributed memories.

  8. DSM architecture-1 • DSM: • Ease of programming and portability • Scalable with very high computing power

  9. DSM architecture-2 • Cluster based architecture

  10. Comparison of IPC paradigms

  11. Types of DSMs • Hardware level DSM • Software level DSM • Hybrid level DSM

  12. Advantages of DSM • Simple abstraction • Improved portability of distributed application programs • Provides better performance in some applications • Large memory space at no extra cost • Better than message passing systems

  13. Hardware DSM

  14. Hardware architectures • On chip memory • Bus based multiprocessor • Ring based multiprocessor • Switched multiprocessor

  15. On chip memory

  16. Bus based multiprocessor • Use bus arbitration mechanism

  17. Consistency protocols

  18. Cache consistency protocol • Properties: • Consistency is achieved since all caches do us snooping • Protocol is built into MMU • The algorithm is performed in one memory cycle

  19. Memnet DSM architecture • Shred memory : • Private areas • Shared areas

  20. Memnet: Node memory

  21. Comparison • The major difference between bus based and ring based multiprocessors is that the former are tightly coupled while the latter are loosely coupled. • Ring based multiprocessors are almost hardware implementation of DSM.

  22. Switched multiprocessorMultiple clusters interconnected by a bus offer better scalability • Example : Dash system

  23. Design Issues In DSM

  24. DSM design issues • Granularity of sharing • Structure of data • Consistency models • Coherence protocols

  25. Granularity • False sharing • Thrashing

  26. DSM structure • Organization of data items in the shared memory

  27. Consistency models • Refers to how recent the shared memory updates are visible to all the other processes running on different machines

  28. Strict consistency • Strongest form of consistency

  29. Sequential consistency • All processors in the system observe the same ordering of reads and writes which are issued in sequence by the individual processors

  30. Causal consistency • Weakening of sequential consistency for better concurrency • Causally related operation is the one which has influenced the other operation

  31. PRAM consistency • Pipelined Random Access Memory consistency • Write operations performed by a single process are seen by all other processes in the order in which they were performed just as if these write operations were performed by a single process in a pipeline. • Write operations performed by different processes may be seen by different processes in different orders.

  32. Processor consistency • Adheres to the PRAM consistency • Constraint on memory coherence • Order in which the memory operations are seen by two processors need not be identical, but the order of writes issued by each processor must be preserved

  33. Weak consistency • Use a special variable called the synchronization variable

  34. Properties of the weak consistency model • Access to synchronization variables is sequentially consistent • Only when all previous writes are completed everywhere, access to synchronizations variable is allowed • Until all previous accesses to synchronization variables are performed, no read write data access operations will be allowed.

  35. Release consistency • Synchronization variables: acquire and release • Use barrier mechanism

  36. Eager Release Consistency

  37. Lazy Release Consistency

  38. Entry consistency • Use acquire and release at the start and end of each critical section, respectively. • Each ordinary shared variable is associated with some synchronization variable such as a lock or barrier. • Entry consistency (EC) is similar to LRC but more relaxed; shared data is explicitly associated with synchronization primitives and is made consistent when such an operation is performed

  39. Scope consistency • A scope is a limited view of memory with respect to which memory references are performed

  40. Comparison of consistency models-1 • Most common: sequential consistency model

  41. Comparison of Consistency models-2 • Based on efficiency and programmability

  42. Coherence protocols • Specifies how the rules set by the memory consistency model are to be implemented

  43. Coherence algorithms • Maintain consistency among replicas

  44. Multiple Reader/ Multiple Writer algorithm • Uses twin and diff creation technique

  45. Write Protocols for consistency • Write Update (WU) • Write Invalidate (WI) protocols

  46. Issues In Implementing DSM Systems

  47. Issues • Thrashing • Responsibility of DMS management • Replication v/s migration • Replacement strategy

  48. Thrashing • False sharing • Techniques to reduce thrashing: • Application controlled lock • Pin the block to a node for specific time • Customize algorithm to shared data usage pattern

  49. Responsibility for DSM management • Algorithms for data location and consistency management: • Centralized manager algorithm • Broadcast algorithm • Fixed Distributed manager algorithm • Dynamic distributed manager algorithm

  50. Centralized Manager algorithm

More Related