IMPAC2T: Integrated Management of Power-Aware Computation and Communication Technologies

1. Integrated Management of Power Aware Computation and Communication Technologies Nader Bagherzadeh, Pai H. Chou, Scott Jordan, Fadi KurdahiUniversity of California, Irvine, ECE Dept. Jean-Luc GaudiotUniversity of Southern California, EE-Systems Nazeeh Aranki, Nikzad “Benny” ToomarianJet Propulsion Laboratory

2. What is IMPAC2T? • Hardware/software codesign tool • for power aware designs • bring together many of the best ideas for power management • design space exploration at the system level • System integration • component-based • interface synthesis • power manager synthesis • Power-aware components • parameterizable components library • wrapper around commercial off-the-shelf components

3. Project Participants • UC Irvine - Design tools • Nader Bagherzadeh • Pai Chou • Scott Jordan • Fadi Kurdahi • USC - Architectural power optimization • Jean-Luc Gaudiot • JPL - Applications and benchmarking • Nazeeh Aranki • Nikzad “Benny” Toomarian

4. behavioral system model high-level components composition operators parameterizable components system architecture busses, protocols Quad Chart Behavior Innovations high-level simulation functional partitioning & scheduling • Component-based power-aware design • Multi-power component aggregation • Power-aware reconfigurable architectures • Protocol-based power management • Global power policy optimization • Static & dynamic configurability for power Architecture mapping system integration& synthesis static configuration dynamic powermanagement Impact System Modeling Coordination Synthesis Architecture Definition Static Partitioning Component partitioning Authoring Tool v1.0 Dynamic Partitioning Simulator v1.0 Component Partitioning • Fully exploit off-the-shelf components • Unified functional/power correctness • Confidence in complex design points • Rapid turnaround time to architecture • Power protocol for massive scale Start End 2Q 00 2Q 02 2Q 01 Kickoff Power Management Design Techniques PCL definition Simulatable components Benchmark Identification Component Simulator PCL benchmarking Synthesizable components System Benchmarking

5. Applications Past Missions Future Missions Power aware technologies are essential for future deep space missions

6. Challenges for the X2000 • Design goals • Low power and high performance designs • Low activation rates and power management • X2000 target is 10-20x reduction in power • Design for technology scaling. • Design for long-term survivability • Systems engineering methodology • Design, simulation, verification and synthesis. • Use design automation / integration tools.

7. PA System Architecture The NASA X2000 Avionics System high-rateinput symmetric multiprocessor modules reconfigurable hardware blocks communication module (CDMA) (camera) high-speed bus (e.g. IEEE 1394) low-speed bus (e.g. I2C ) bus power controller microcontroller-directed subnet - power regulations & control - analog telemetry sensors - safety inhibits - valve & pyro drive altimeter subnet

8. Previous Work • Design Tools • System-Level: the Chinook HW/SW codesign tool • Architectural synthesis (w/ physical design considerations) • Components • Reconfigurable computing: the MorphoSys Chip • Parameterizable components: PCL • Simultaneous MultiThreadingvs. Chip MultiProcessing • Architectural platform • Segmented bus X-2000, Mars Pathfinder • Configurable SMP

9. Background: MorphoSys Project Advanced RISC Processor MorphoSys • Reconfigurable processor array • MIPS-like RISC processor • High-bandwidth data interface • 100 MHz clock • 0.35µm 4metal CMOS • Software support • Platform for dynamic power management Reconfigurable Processor Array System Bus Instr./Data Cache (L1) High Bandwidth Data Interface External Memory (e.g. SDRAM, RDRAM)

10. Background: Chinook project • Component-based HW/SW codesign framework • Specification, simulation, synthesis • Motivated by IP reuse, system integration • Problem: IP Reuse forces modification • Reason: components have hardwired coordination protocols • Approach • Adaptable components • Separate coordination protocolsfrom components • Benefits • Reuse without modification • Enable system-level optimizations

11. s i y i i y s i joystick override idle subsuming i bumper escape s s i sonar avoid s subsuming yielding F B i wheels y i W B W sensors actuators decision modules decision composition Example protocol: Subsumption • Must handle three cases: • Subsuming, yielding, idle • Hardwired protocol • Generalization: • Adaptable components (by mode mapping) • Separate protocols & components y s i y s i +subsuming y subsumption interface idle subsuming yielding s i Bumper process y release W F B W T 2s F B T s i bump 45d +B +W

12. Power-aware coordination • Protocols • Coordinate power usage • e.g. peak power, resource arbitration • Multiple versions of given algorithm • Components • Adaptable to different power management policies, not hardwired • Usable in new applications even if not designed to be power aware! • Synthesis • Coordination controller (“mode manager”) • Depends on architectural mapping.

13. mode manager Architectural mapping • Single processor or multiple processors • Multiple mappings to an architecture modal processes

14. mode manager Distributed mode managers • Automatically partitioned among processors • synthesized control communication • comm. tradeoffs: synchronization, replication modal processes

15. high-level components composition operators behavioral system model parameterizable components system architecture busses, protocols IMPAC2T overview Behavior high-level simulation functional partitioning & scheduling Architecture mapping system integration& synthesis static configuration dynamic powermanagement

16. Innovations • Specification • Component-based power-aware design • Protocol-based power management • Multi-power component aggregation • Architecture • Power-aware reconfigurable architectures • Static & dynamic configurability for power • Global power policy optimization • Synthesized power manager (centralized and distributed)

17. Impact • Productivity • Fully exploit off-the-shelf components • Rapid turnaround time to architecture • Massive Scalability • Protocol based power management • System architecture platform • Robust methodology • Unified functional/power correctness • Confidence in complex design points

18. Technology Transition • JPL • first users of this tool • Commercialization • startup company

19. Milestones System Modeling Coordination Synthesis Architecture Definition Static Partitioning Component partitioning Authoring Tool v1.0 Dynamic Partitioning Simulator v1.0 Component Partitioning 2Q 02 2Q 00 2Q 01 Kickoff Power management design techniques PCL definition Simulatable components Benchmark Identification Component Simulator PCL benchmarking Synthesizable components System Benchmarking

20. Conclusion • Co-design framework • Component-based parameterization and integration • Commercial off-the-shelf and DARPA-community designs(ND’s Morphable architecture) • Supports high-level coordination, dynamic management of power/performance • Design space exploration tool for DARPA community • JPL, DADS http://www.ece.uci.edu/impacct/

21. Partitioning & Integration • Static partitioning • Map behavioral description onto the elements in the architecture • Component => processor • Channel => bus • Dynamic partitioning • Multi-version components • Applicable to hardware, software, and mixed • Complements middleware / object migration • System integration mechanisms • Synthesized/optimized power-timing coordination controller • Mode managers + coordination protocols • High-level knowledge enables tradeoffs and optimization

22. Simulation and Analysis • System level validation and analysis • Components • Coordination protocols • Systems • Support the exploration of design space • Metrics: cost, area, performance, power • Must capture low level and data type effect • Interaction with simulators • Back annotation interface to (commercial) low-level simulators

23. Parameterizable Component Library • Levels of abstraction • Analyzable • Simulatable • Synthesizable • Synthesized • Component characterization • Register level decomposition • Analysis of power consumption • VLSI layout size • Performance by simulation

24. ComponentEvaluation BehavioralComposition ArchitecturalExploration PremissionConfiguration Dynamic powermanagement Parameterized component libraryAccurate hw/sw power estimationPower-aware microarchitecture Higher-order operators for power coordinationMulti-implementation componentsSynthesis/optimization of coordination controllers System-level simulation and analysisPower-aware hw/sw partitioning Scalable, reconfigurable multiprocessor arch.Synthesized power manager for mission planning Arch. support for hw/sw process migrationPre-mission power/real-time scheduling Power-Aware Design Methodology Support Provided Design Stage

25. Outline • Research Organization • Quad Chart • Previous Relevant Efforts by PI’s • Proposed Work • Innovations • Application Domain • Technology Transfer

26. Tool Flow Each high level component encapsulates one or more low level components Low level components have detailed power estimates