1 / 8

Front-End Interface, GBT-FPGA Resource Usage Optimization

Learn about clocking schemes and clock domain issues in GBT-FPGA utilization for efficient front-end interfaces. Discover solutions for realistic resource allocation and clock synchronization challenges in your design.

donaldcross
Télécharger la présentation

Front-End Interface, GBT-FPGA Resource Usage Optimization

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Front-End Interface, GBT-FPGA Resource Usage Optimization Erno DAVIDWigner Research Center for Physics (HU) 26 January, 2016

  2. PCIe40 Board Clock Paths 2

  3. GBT Bank Clocking Scheme CRU Arria 10 FPGA 240MHz 10G PON Transceiver TTS(ONU) 10G PON REFCLK 240MHz 40MHz External PLL + Jitter Cleaner + Fanout Buffer 40 MHz 184 bit 0 7 3 120MHz 40MHz IOPLL GBT Transmitters Bank 0 GBT Gear Box Downlink Logic Bank 0 250MHz 6 x 40 bit 80 bit GBT_BANK_0_REFCLK 120 MHz 256 bit TX SCA 6 x 2 bit TX GBTx GBT Bank 0 – Link 0 .. 5 (Consist 6 adjacent bonded Arria 10 transceiver) 2 bit 120MHz 40MHz IOPLL GBT Gear Box Uplink Logic Bank 0 250MHz GBT Receivers Bank 0 80 bit 6 x 40 bit 256 bit 6 x RX SCA 2 bit RX GBTx 2 bit The number of GBT Banks is equal to GBT Links / 6 3

  4. Core CRU Framework Clock Domains • GBT-FPA clocking resources per x6 (in bonded mode): • GBT reference clock (120 MHz) • ATX PLL (120 MHz -> 2400 MHz) for 4.8 Gbps GBT transceivers • Transceiver TX clock (TX_WORDCLOCK, 120 MHz) • IOPLL (120 MHz -> 40 MHz) • GBT TX_FRAMECLOCK 40 MHz • Transceiver RX clock (RX_WORDCLOCK, 120 MHz) • IOPLL (120 MHz -> 40 MHz) • GBT RX_FRAMECLOCK 40 MHz • PCIe Hard IP clocking resources per Endpoint: • 100 MHz PCIe reference clock • ATX PLL (100 MHz -> 4000 MHz) for Gen3 8 Gbps transceivers • 250 MHz PCIe user clock • TTS 10G PON clocking resources: • 120 MHz reference clock for the 9.6 Gbps PON Downlink • ATX PLL (120 MHz -> 4800 MHz) for 9.6 Gbps PON transceiver • 40 MHz PLL for reconstructing the LHC clock Clock Domains: 5 PLLs: 3 Clock Domains: 2 PLLs: 1 Clock Domains: 2 PLLs: 2 4

  5. Problems and Solutions in Current Design • Our resource usage (ALMs and FFs) is not realistic: • Solution: Use more realistic firmware which works in hardware • Large number of GBT-FPGAs require huge amount clocking resources (PLLs, global clock lines): • Solutions: • Use different clocking scheme, or different bonding mode – Is it going to degrade our jitter? • Eliminate the 40 MHz clock domain from the GBT-FPGA design • How to inject the raw TTS bits into each GBT Tx clock domain properly if we have 360 / 20 degree phase uncertainty between the 10G PON recovered clock and the GBT Tx clock: • Solutions: • Calculate the phase difference and reset the transceiver if it is not OK? 5

  6. GBT-FPGA Arria 10 Resource Usage (1) 6

  7. GBT-FPGA Arria 10 Resource Usage (1) 7

  8. GBT-FPGA Arria 10 Resource Usage (1) 8

More Related