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An ASIC Design methodology with Predictably Low Leakage, using Leakage-immune Standard Cells

An ASIC Design methodology with Predictably Low Leakage, using Leakage-immune Standard Cells. Nikhil Jayakumar, Sunil P Khatri ISLPED’03. outline. Introduction Research about leakage power reduction State assignment and leakage power Approach and design methodology Result Conclusion. V.

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An ASIC Design methodology with Predictably Low Leakage, using Leakage-immune Standard Cells

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  1. An ASIC Design methodology with Predictably Low Leakage, using Leakage-immune Standard Cells Nikhil Jayakumar, Sunil P Khatri ISLPED’03

  2. outline • Introduction • Research about leakage power reduction • State assignment and leakage power • Approach and design methodology • Result • Conclusion

  3. V - - V V V gs T off W ds - ( ) ( ) = - nv v I I e ( 1 e ) t t 0 ds L G D S B Introduction • Importance of leakage currents control • Leakage current Ids: • Voltage scaling and threshold voltage scaling

  4. Leakage reduction • Source biasing • Using body effect case Vt↑ but performance ↓ • Stack effect • Direct Vt manipulation • Dual Vt partition • MTCMOS • VTCMOS

  5. Leakage reduction • Source biasing • Using body effect case Vt↓buperformance↑ • Stack effect • Direct Vt manipulation • Dual Vt partition • MTCMOS • VTCMOS

  6. State & voltage assignment(DAC 03) • State dependence of a leakage current • Find the best input vector for standby state • accuratly estimate Leakage of designs

  7. State & voltage assignment(DAC 03) • State dependence of a leakage current

  8. State & voltage assignment(DAC 03) • Without any state assignment 0.31ns 0.36ns 9.6nA 4.7nA

  9. State & voltage assignment(DAC 03) • Optimal input state with Vt assignment 0.31ns 0.31ns 9.6nA 0.99nA

  10. MTCMOS & state assignment • MTCMOS better than traditional standard cells design • Not support predictable leakage currents • Two variants of standard cell • H variant for output “high” • L variant for output “low”

  11. MTCMOS & state assignment L variant of 3-NAND H variant of 3-NAND

  12. Layout floorplan of HL gates L variant of a standard-cell Regular standard-cell H variant of a standard-cell

  13. Design flow Standard cell library Traditional mapping using regular standard cells Determine a set of primary input assignment Simulate to find output of each gate Modified Standard cell library Replace each gate by its output value Place and route

  14. Experimental results HL cell versus MT cell

  15. Experimental results HL/MT cells versus regular cells

  16. Leakage/area/delay comparison • Precisely estimate leakage

  17. Leakage/area/delay comparison • Using exact timing analysis by run “sense” in SIS • HL 10% MT 12.5% delay overhead

  18. Leakage/area/delay comparison • Using SE to P&R • HL 11-21% overhead but 17% less than MTCMOS

  19. Conclusions • Low and predictable leakage value • Better algo. To determine the best primary input vector • Improve overhead

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