Micro transductors ’08 Low Leakage VLSI Design

1. Micro transductors ’08Low Leakage VLSI Design Dr.-Ing. Frank Sill Department of Electrical Engineering, Federal University of Minas Gerais, Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil franksill@ufmg.br http://www.cpdee.ufmg.br/~frank/

2. Agenda • Recap • Trends • Leakage components • Leakage reduction • On technology level • On transistor and gate level • On architecture level Micro transductors ‘08, Low Leakage

3. Recap: Problems of Power Dissipation • Continuously increasing performance demands • Increasing power dissipation of technical devices • Today: power dissipation is a main problem • High Power dissipation leads to: • Reduced time of operation • Higher weight (batteries) • Reduced mobility • High efforts for cooling • Increasing operational costs • Reduced reliability Micro transductors ‘08, Low Leakage

4. R e g Functional unit clock disable Recap: Clock Gating • Most popular method for power reduction of clock signals and functional units • Gate off clock to idle functional units • Logic for generation of disable signal necessary • Higher complexity of control logic • Higher power consumption • Critical timing critical for avoiding of clock glitches at OR gate output • Additional gate delay on clock signal Source: Irwin, 2000 Micro transductors ‘08, Low Leakage

5. Register Register Register Register Recap: Parallel Architecture Supply voltage: VN ≤ Vref N = Deg. of parallelism Each copy processes every Nth input, operates at reduced voltage Comb. Logic Copy 1 fclk/N Comb. Logic Copy 2 Output Input N to 1 multiplexer fclk/N fclk Comb. Logic Copy N Multiphase Clock gen. and mux control fclk/N CK Source: Agarwal, 2007 Micro transductors ‘08, Low Leakage

6. CLK A/N A/N A/N Data Data Recap: Pipelined Architecture • Reduces the propagation time of a block by factor N  Voltage can be reduced at constant clock frequency • Constant throughput • Functionality: Area A CLK CLK Micro transductors ‘08, Low Leakage

7. B Segmented Bus B Recap: Busses • Bus segmentation • Another way to reduce shared buses • Control of bus segment by controller blocks (B) Shared Bus Source: Evgeny Bolotin – Jan 2004 Micro transductors ‘08, Low Leakage

8. Recap: Adaptive DVS • Task with 100 ms deadline, requires 50 ms CPU time at full speed • Normal system gives 50 ms computation, 50 ms idle/stopped time • Half speed/voltage system gives 100 ms computation, 0 ms idle • Same number of CPU cycles but: E = C (VDD/2)2 = Eref / 4 • Dynamic Voltage Scaling adapts voltage to workload T1 T2 T1 T2 Same work, lower energy Speed Idle Task Task Time Time Micro transductors ‘08, Low Leakage

9. Recap: Processor Modes Source: Transmeta Micro transductors ‘08, Low Leakage

10. 1000 1000 mAh (Standard Capacity) 800 600 Capacity (mAh) 400 125mA 200 ( Rated Current) Discharge current (mA) Available Charge (mA) time Discharge Current (mA) idle time Battery aware design • Non-linear effects influence life time of batteries • “Rate Capacity” • If discharging currents higher than allowed real capacity goes under nominal capacity • “Battery Recovery” • Pulsed discharge increases nominal capacity • Based on recovery times • (as long there is no rate capacity effect) Source: Timmermann, 2007 Micro transductors ‘08, Low Leakage

11. Manufacturing Development Research Carbon Nanotube FET 5 nm 50 nm 30 nm Nanowire 35 nm 20 nm 10 nm S D S Metal Gate III-V High-k Tri-Gate G Si Substrate Trends Technology Generation 90 nm 65 nm 45 nm 32 nm 2004 2006 2008 2010 2012+ SiGe S/D Strained Silicon SiGe S/D Strained Silicon Micro transductors ‘08, Low Leakage

12. Trends cont‘d Power Dissipation by Leakage currents Dynamic Power Dissipation Source: S. Borkar (Intel), ‘05 Micro transductors ‘08, Low Leakage

13. Gate-width W tox SiO2 gate oxide L (good insulator, eox = 3.9 Gate length tox – thickness of oxide layer Recap: Transistor Geometrics polysilicon gate n+ n+ p-type body Source: Rabaey,“Digital Integrated Circuits”,1995 Micro transductors ‘08, Low Leakage

14. Gate Drain Source Subthreshold Leakage • Threshold Voltage • Transistor characteristic • If: „Gate-Source“-Voltage Vgshigher than Vth • Channel under Gate • Current between Drain and Source • If: Vgslower than Vth • (ideal) No current • Subthreshold leakage Isub • Leakage between Drain and Source when Vgs < Vth • Based on: • Short Channels • Diffusion • Thermionic Emission Isub Micro transductors ‘08, Low Leakage

15. Subthreshold Leakage cont’d Short-channel device Transistor is conducting Log (Drain current) Isub NMOS-Transistor Gate voltage 0 Vth’ Vth Source: Agarwal, 2007 Micro transductors ‘08, Low Leakage

16. IOFF at 1100C Isub at 250C Temperature dependence • Based on Thermionic Emission: subthreshold leakage Isub increases with temperature Source: Chatterjee, Intel-labs 70nm16x 130nm6x Micro transductors ‘08, Low Leakage

17. Gate Oxide Leakage • Tunneling effect • Electromagnetic wave strike at barrier: • Reflection + Intrusion into barrier • If thickness is small enough: • Wave interfuse barrier partially: (Electrons tunnel through Barrier) • Gate oxide leakage Igate • In Nanometer-Transistors, where Tox<2nm • Electrons tunnel through gate oxide • Leakage current Igate Micro transductors ‘08, Low Leakage

18. Gate Oxide Thickness at 45 nm Micro transductors ‘08, Low Leakage

19. Components of Gate Oxide Leakage: Tunneling currents through overlap regions (gate-drain Igso, gate-source Igdo) Tunneling currents into channel (gate-drain Igis, gate-source Igcd) Tunneling currents between gate and bulk (Igb) Gate Oxide Leakage cont’d Micro transductors ‘08, Low Leakage

20. Drain Induced Barrier Lowering (DIBL) Vgs > Vth Vgs < Vth Height of curve = Potential barrier Changed by gate voltage • Electrons have to overcome potential barrier to enter the channel • Ideal: Potential barrier is only controlled by gate voltage Micro transductors ‘08, Low Leakage

21. Drain Induced Barrier Lowering cont’d Short-channel transistor (L < 180 nm) Long-channel transistor (L > 2 µm) • At short channel transistors potential barrier is also affected by drain voltage  If Vds = VDD Transistors can start to conduct even if Vgs < Vth Lowering of potential barrier Micro transductors ‘08, Low Leakage

22. IHCI IGIDL Ipn Ipt Further Leakage Components • Reverse bias pn junction conduction Ipn • Gate induced drain leakage IGIDL • Drain source punchthrough IPT • Hot carrier injection IHCI Micro transductors ‘08, Low Leakage

23. Leakage Dependencies • Leakage depends on: • Gate Width (Isub, Igate) • Gate Length (Isub) • Gate Oxide Thickness (Igate) • Threshold Voltage (Isub) • Temperature (Isub) • Input state (Igate) Micro transductors ‘08, Low Leakage

24. Recap: Levels of Optimization Micro transductors ‘08, Low Leakage nach Massoud Pedram

25. Idle states (passive) Components have nothing to do Active states Components are working Approaches to Reduce Leakage Approaches for different states Micro transductors ‘08, Low Leakage

26. Approaches on Technology Level Retrograde well • Different Concentration of dopant (implanted) inside the substrat • Lowest concentration: near the channel • Lower subthreshold leakage • Highest concentration: near the bulk connection • Reduced possibility for punch-through Micro transductors ‘08, Low Leakage

27. Approaches on Technology Level cont’d • Halo Implants • High doped regions near source and drain areas • Reduced Drain Induced Barrier Lowering • Offset Spacer • Silicon nitride placed beside gate area • Reduced overlap regions • Reduced gate leakage through overlap regions • But: Increased channel resistance Micro transductors ‘08, Low Leakage

28. Power & Delay Dependence of Vth w.o. gate leakage Source: Sakurai, ‘01 Micro transductors ‘08, Low Leakage

29. Influence of Threshold Voltage Vth • Threshold Voltage Vth: • Influence on sub-threshold leakage Isub • Influence on delay of logic gates Isub Delay Micro transductors ‘08, Low Leakage

30. Influence of Gate Oxide Thickness Tox • Gate oxide Thickness Tox: • Influence on gate oxide leakage Igate • Influence on delay Delay Igate Micro transductors ‘08, Low Leakage

31. Recap: Data Paths • Data propagate through different data paths between registers (flipflops - FF) • Paths mostly differ in propagation delay times • Frequency of clock signal (CLK) depends on path with longest delay critical path Paths Path Micro transductors ‘08, Low Leakage

32. G1 ready with evaluation all inputs of G2 all Inputs of G1 arrived arrived delay of G1 Recap: Slack A B Y C time Slack for G1 Micro transductors ‘08, Low Leakage

33. Dual-Vth / Dual-Tox Two different gate types: • Gates consist of „low-Vth“- or „low-Tox“-transistors • Low threshold voltage or thin gate oxide layer • For critical paths • High leakage “LVT / LTO”-Gates • Gate consist of „high-Vth“- „high-Tox“-transistors • High threshold voltage or thick gate oxide layer • For uncritical paths • Low leakage “HVT / HTO”-Gate • Leakage reduction at constant performance (no level converter necessary) Micro transductors ‘08, Low Leakage

34. Performance at different Dual-Vth Measured at NAND2 BPTM 65nm Technology Micro transductors ‘08, Low Leakage

35. Leakage Isub at different Dual-Vth Measured at NAND2 BPTM 65nm Technology Micro transductors ‘08, Low Leakage

36. LVT - or LTO - Gates HVT - or HTO - Gates Dual-Vth / Dual-Tox Example Critical Path Micro transductors ‘08, Low Leakage

37. Dual-Vth / Dual-Tox at Transistor Level Better leakage reduction possible Much higher effort in design phase “low-Vth” or “low-Tox” transistors “high-Vth” or “high-Tox” transistors Uncritical path Critical path Micro transductors ‘08, Low Leakage

38. Simultaneous Vt, Size and Vdd Assignment • Leakage reduced through either increasing Vth or lowering VDD • Lowering Vdd also reduces dynamic power • Topological constraints on VDD assignment • Requires use of voltage level converters • Assign VDD first then perform sizing/Vth assignment Begin Topology Based Slack Distribution Delay Minimize All Paths Sensitivity Based Slack Distribution Change VDD of Gates with Sufficient Slack Change Gates With Sufficient Slack P  Source: [Nguyen, et al., ISLPED03] End Micro transductors ‘08, Low Leakage

39. Stack Effect • Transistor stack: at least two transistor from same type (NMOS or PMOS) in a row • Based on behavior of internal nodes:  The more transistors are non-conducting (off) the lower the leakage Source: Roy, “Lecture” Micro transductors ‘08, Low Leakage

40. sleep Vdd Virtual Vdd Virtual Vss Vss sleep Sleep Transistors • Idea: Insertion of additional transistors between logic block and supply lines • This transistors: connect with SLEEP-signal • If circuit has nothing to do: • SLEEP signal is active: Stack effect (additional off transistor in row to other) • If sleep transistors are High-Vth: approach also called Multi-Threshold CMOS (MTCMOS) • Mostly insertion only of 1 Transistor Low-Vth logic cells Source: Kaijian Shi, Synopsys Micro transductors ‘08, Low Leakage

41. VVDD1 domain VVDD2 domain Sleep Transistors: Realization Ring style sleep transistor implementation Global VDD VDD • Sleep transistors are placed around each VVDD island Source: Kaijian Shi, Synopsys Micro transductors ‘08, Low Leakage

42. Sleep Transistors: Realization cont’d Grid style sleep transistor implementation Global VDD VDD VVDD2 VVDD1 VVDD2 VVDD1 VVDD2 VVDD1 • VDD network cross chip; VVDD networks in each gating domain • Sleep transistors are placed in grid connecting VDD and VVDDs Source: Kaijian Shi, Synopsys Micro transductors ‘08, Low Leakage

43. Sleep Transistors: Problems • Sleep transistor can be modeled as resistor R • In active mode (gate is working) • Current I through sleep transistor • Voltage Vx drop over resistor • Output voltage reduced to VDD-Vx Current I is not leakage current! I is discharging current of load capacitance Reduced Delay (of following blocks) Micro transductors ‘08, Low Leakage

44. Stackforcing • Simple method of using stack effect  Increasing stack by splitting transistors  Cin stays constant  Only one technology is needed  Area is (almost) the same  Drive strength (drain-source current) is reduced  delay goes down Micro transductors ‘08, Low Leakage

45. Stackforcing cont’d Normalized delay No Stackforcing Normalized Isub Source: Narendra, et al., ISLPED01 Micro transductors ‘08, Low Leakage

46. Input Vector Control (IVC) • Leakage of gate depends on input vector Micro transductors ‘08, Low Leakage

47. Input Vector Control cont’d • Every circuits is input vector with minimum leakage • Idea: If design is in passive mode • SLEEP signal gets active • Sleep vector is applied Micro transductors ‘08, Low Leakage

48. Pin Reordering BPTM, 65 nm technology • Gate Leakage in stack depends on input vector • Same logic input vector (amounts of ‘0’ and ‘1’ is equal) → can result in different leakage • If input probability is know  reorder pins so that highest probable state has minimum gate leakage Micro transductors ‘08, Low Leakage

49. 5 8 4 delay normalized delay normalized power 3 5 2 leakage power 1 -0,5 -1,5 -1 0 0,5 Back-gate Bias VBS [V] Variable Threshold CMOS (VTCMOS) • Threshold voltage Vth depends on bulk voltage (Vbs) • As leakage (Isub) and delay depends on Vth  Delay and leakage (Isub) can be controlled over Vbs • VTCMOS: dynamic adjustment of frequency and Vth through back-gate bias (=Vbs) control Micro transductors ‘08, Low Leakage

50. VTCMOS: VTH-hopping scheme Vth_high_enable Vth_low_enable VBSP1 VBSP Vth - controller VBSP2 VDD Frequency- controller VBSH1 GND fclk1 or fclk2 VBSH2 VBSH Power Control Block Vth - Selector Target Processor Source: NOSE et al.: - VTH HOPPING SCHEME Micro transductors ‘08, Low Leakage