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A VPI-based IP Core Serial Fault Simulation and Test Generation Methodology

A VPI-based IP Core Serial Fault Simulation and Test Generation Methodology. Pedram A. Riahi† Zainalabedin Navabi† Naghmeh Karimi‡ Fabrizio Lombardi†. ECE Department, Northeastern University† ECE Department, University of Tehran‡ IEEE-NATW 2003. Introduction. System-on-Chip (SOC)

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A VPI-based IP Core Serial Fault Simulation and Test Generation Methodology

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  1. A VPI-based IP Core Serial Fault Simulation and Test Generation Methodology Pedram A. Riahi† Zainalabedin Navabi† Naghmeh Karimi‡ Fabrizio Lombardi† ECE Department, Northeastern University† ECE Department, University of Tehran‡ IEEE-NATW 2003

  2. Introduction • System-on-Chip (SOC) • SOC Testing • Present Solutions • Hardware Description Languages (HDLs) • SOC Testing using VPI • Results on ISCAS Benchmarks • Conclusion and Future Works IEEE-NATW 2003

  3. System-on-Chip (SOC) • Complex Functional Blocks • System-on-Board • Core: • μP/μC • DSP • Memory • Function-Specific • Logic Element • Communication Peripheral • Analog Device IEEE-NATW 2003

  4. System-on-Chip (SOC) • Reusable Cores • Core Types: • Soft (Synthesizable) • Firm • Hard • Intellectual Property (IP) • In-house cores IEEE-NATW 2003

  5. SOC Testing • Traditional Test Methods • Core-Level Testing • Design For Test (DFT) • Automatic Test Pattern Generation (ATPG) • Chip-Level Testing • Justifying Test Sequences • Propagating Test Response IEEE-NATW 2003

  6. Present Solutions • Core-Level Testing • System Chip’s Functional Test • Direct Access (I/O Muxing) • Local Boundary-Scan or Collar Register • Full-Scan / Built-in-Self-Test (BIST) • Proprietary Solution • Chip-Level Testing IEEE-NATW 2003

  7. Present Solutions • Full-Scan / Boundary-Scan (FScan-BScan) Full- or Partial-Isolating Rings / Control Points FScan-BScan IEEE-NATW 2003

  8. Present Solutions • Full-Scan / Test Bus (FScan-TBus) • Test Bus / Boundary-Scan Chain IEEE-NATW 2003

  9. Present Solutions • Binary Decision Diagram (BDD) • Partial Netlist / Partial Boundary Scan IEEE-NATW 2003

  10. Present Solutions • Core Transparency FPath HScan IEEE-NATW 2003

  11. Present Solutions • IEEE P1500 • BIST • Chip-Level Testing • Parallel Direct Access • Serial Scan Access • Functional Access IEEE-NATW 2003

  12. Hardware Description Languages (HDLs) • VHDL • Verilog • Procedural Interfaces: • VHPI • VPI • Cadence Verilog-XL • C Platform IEEE-NATW 2003

  13. SOC Testing with VPI • VPI-based Test Environment • VPI-based Fault Simulation • Single Stuck-at Fault • Serial • VPI-based Test Generation • Random Pattern IEEE-NATW 2003

  14. SOC Testing with VPI • Proposed VPI Task Arguments for Fault Simulation • SFS_faultlist • Node Type: reg, net • Node Name: ~.module_name/node_name • Stuck-at: sa0, sa1 • Not Injected • Injected but not Detected • Partially Detected • Detected • Status: 0, 1, Z, X • SFS_faultinjection, SFS_faultrelease • SFS_updatefaultlist[one, two, three] IEEE-NATW 2003

  15. SOC Testing with VPI • Proposed VPI Task Arguments for Test Generation • SFS_faultcoverage • SFS_morefault • SFS_decide • SFS_readstatus, SFS_restorestatus • SFS_randomvector • SFS_saveoutput, SFS_compareoutput • SFS_savevector, SFS_report IEEE-NATW 2003

  16. SOC Testing with VPI • Initialization doread := true; $SFS(faultlist); while !($SFS(faultcoverage, coverage) satisfied) { if (doread) $SFS(readstatus); $SFS(randomvector, depth); $readmem; for (all vectors) { Apply Vector; $SFS(savevector); } … Fault Injection and Simulation … Decide } $SFS(report); IEEE-NATW 2003

  17. SOC Testing with VPI • Fault Injection and Simulation Lindex := 0; while ($SFS(morefault)) { $SFS(restorestatus); $SFS(faultinjection); flag := true; for (all vectors and flag) { Apply Vector; if ($SFS(compareoutput) == detected) { $SFS(updatefaultlistone); flag := false; Lindex := Largest index; } $SFS(faultrelease); } IEEE-NATW 2003

  18. SOC Testing with VPI • Decide if ($SFS(decide, limit) == GOOD) { $SFS(savevector); $SFS(updatefaultlisttwo); if (Lindex > depth) { $SFS(restorestatus); for (all vectors that index < Lindex) Apply Vector; } doread := true; } else { $SFS(restorestatus); $SFS(updatefaultlistthree); doread := false; } IEEE-NATW 2003

  19. Results on ISCAS Benchmarks • PARWAN • HITEC • ISCAS85/89 Netlist Files • VPI • ISCAC85/89 Verilog Codes • Fault Collapsing • Fan-outs IEEE-NATW 2003

  20. Results on ISCAS Benchmarks IEEE-NATW 2003

  21. Results on ISCAS Benchmarks IEEE-NATW 2003

  22. Results on ISCAS Benchmarks IEEE-NATW 2003

  23. Conclusion and Future Works • A Test Methodology for SOC IP Core Fault Simulation and Test Generation • Serial Fault Simulation • Parallel or Deductive Fault Simulation • Mixed-Level Fault Simulation • Module-based • Process-based • Random Pattern Test Generation • Reaching Higher Performance using VPI Built-in Features IEEE-NATW 2003

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