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Electronics and Readout for CEDAR Research: A Comprehensive Analysis

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elewa
9 diapositives · 207 Views · Oct 15, 2014

This research focuses on developing electronics for CEDAR to meet specific signal, noise, and amplitude requirements. Survey of radiation-tolerant pre-amplifiers and fast ADCs for efficient readouts in the CEDAR environment.

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Electronics and Readout for CEDAR Research: A Comprehensive Analysis
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  1. Electronics and readout for CEDAR Marian Krivda, Richard Staley University of Birmingham, UK

  2. Requirements • The signal from 1 photoelectron about 2 mV (current flowing into 50 ohms) • amplify by ~10 (=20mV) • noise should be < 0.2 mV • no more than 10 photoelectrons at the same time, so the range should be from mV to hundreds of mV • 8 bits resolution • high rate sampling is needed to detect double pulses at ~2-3 ns interval • Total dose 100 kRad

  3. Survey of radiation tolerant pre-amplifier • ADN2882 (3,5 GHz) - SiGe - transimpedance amplifier with a differential CML output which may be suitable for CEDAR as long as we keep the output operating in the linear region, low noise, power dissipation is 80 mW. We need to add another amplifier as the output voltage will limit before reaching the full-scale range of the ADC. • ADL5542 (50Hz - 6 GHz, 50 Ohm in/out) – InGaP - broadband 20 dB linear amplifier, power consumption 93 mA at 5 V, noise figure 3 dB at 900 MHz • GALI5 from MiniCircuits (DC - 4 GHz) – InGaP - 50 ohm in/out x 10 voltage gain blocks with a bandwidth of 4GHz, radiation tolerant, noise figure of 3.5dB = 1.35nV/rootHz)

  4. Survey of Fast ADC (8-bits) • EV8AQ160CTPY – (can be used either as 4 channel of 1.25GSPS or 2 channels of 2.5GSPS or 1 channel of 5GSPS) – radiation tolerant, can be used directly with pre-amplifier (analog input 500 mVpp), quite expensive (200 EUR/1 pc) • Non radiation tolerant FADC – there is a number of suitable parts, for example, a 2 channel 1GHz FADC (ADC08D1000) that costs $304 (1000 of)

  5. Survey of processor unit 32 x 1 Gs/s TTC

  6. Survey of processor unit - result • Tell1 board is OK only for testing – prototyping • build a new PCBs with newer FPGAs as these have more resources and faster I/O than the Altera Stratix1 used on the TELL1. Altera Stratix GX family has hardware dedicated to building Gb/s links

  7. First possible solutions radhard TA OAP FADC Processor Unit (AlteraStratixGX) ??? EV8AQ160 LVDS receiver ADN2882 typ. 260 mV max. 375 mV 500 mV ??? LVDS links 10 m clock input 2,5 GHz

  8. Second possible solutions radhard TA OAP Processor Unit (AlteraStratix GX) ??? FADC ADN2882 typ. 260 mV max. 375 mV 500 mV ??? Differential twisted pair links 10 m (high quality cable)

  9. First step to do list • Test ADN2882 (choose the right feedback capacitor for stability and bandwidth) • Find out how linear it is with PM signals • Radiation test of pre-amp (and PMTs) in Birmingham, at the synchrotron (the exposure can and will be significantly higher than what it is expected at the CEDAR, so it will be a real test)