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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Low Voltage Low Power Devices. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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  1. ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsLow Voltage Low Power Devices Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC5970-001/6970-001 Lecture 4

  2. Threshold Voltage, Vt Polysilicon gate SiO2 p-type body + + + + + + + + + + + - Depletion region 0 < Vg < Vt + + + + + + + + + + + + + + + + + + + + + + + + + + Vt is a function of: Dopant concentration Thickness of oxide Polysilicon gate SiO2 p-type body + + + + + + + + + + + + + + - • - - - - - - - - - - - - - - - - - - • Depletion region • + + + + + + + + + + + + + • + + + + + + ++ + + + + + Vg > Vt ELEC5970-001/6970-001 Lecture 4

  3. Bulk nMOSFET Polysilicon Vgs Vgd Gate Drain Source W n+ n+ L p-type body (bulk) SiO2 Thickness = tox ELEC5970-001/6970-001 Lecture 4

  4. α-Power Law Model Vgs > Vt and Vds > Vdsat = Vgs –Vt (Saturation region): β Ids = Pc ─ (Vgs – Vt)α 2 where β = μCoxW/L For fully ON transistor, Vgs = Vds = VDD: β Idsat = Pc ─ (VDD – Vt)α 2 T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,” IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 584-594, 1990. ELEC5970-001/6970-001 Lecture 4

  5. α-Power Law Model (Cont.) 400 300 200 100 0 Shockley α-power law Simulation Idsat Ids (μA) Vgs = 1.8V 0 0.3 0.6 0.9 1.2 1.5 1.8 Vds ELEC5970-001/6970-001 Lecture 4

  6. α-Power Law Model (Cont.) 0 Vgs < Vt, cutoff Ids = Idsat×Vds/Vdsat Vds < Vdsat, linear Idsat Vds >Vdsat, saturation Vdsat = Pv(Vgs – Vt)α/2 ELEC5970-001/6970-001 Lecture 4

  7. α-Power Law Model (Cont.) • α = 2, for long channel devices or low VDD • α ~ 1, for short channel devices ELEC5970-001/6970-001 Lecture 4

  8. Power and Delay Power = CVDD2 CVDD 1 1 Inverter delay = ──── (─── + ─── ) 4 Idsatn Idsatp KVDD = ─────── (VDD – Vt)α ELEC5970-001/6970-001 Lecture 4

  9. Power-Delay Product VDD3 Power × Delay = constant × ─────── (VDD – Vt)α Power Delay 0.6V 1.8V 3.0V VDD ELEC5970-001/6970-001 Lecture 4

  10. Optimum Threshold Voltage For minimum power-delay product: 3Vt VDD = ─── 3 – α For long channel devices, α = 2, VDD = 3Vt For very short channel devices, α = 1, VDD = 1.5Vt ELEC5970-001/6970-001 Lecture 4

  11. Leakage VDD IG Ground R n+ n+ Isub IPT ID IGIDL ELEC5970-001/6970-001 Lecture 4

  12. Leakage Current Components • Subthreshold conduction, Isub • Reverse bias pn junction conduction, ID • Gate induced drain leakage, IGIDL due to tunneling at the gate-drain overlap • Drain source punchthrough, IPT due to short channel and high drain-source voltage • Gate tunneling, IGthrough thin oxide ELEC5970-001/6970-001 Lecture 4

  13. Subthreshold Leakage Vgs – Vt Isub = I0 exp( ───── ) nvth Ids 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA Saturation region Subthreshold region Vt 0 0.3 0.6 0.9 1.2 1.5 1.8 V Vgs ELEC5970-001/6970-001 Lecture 4

  14. Normal CMOS Inverter VDD o output input GND SiO2 Polysilicon (input) output GND VDD metal 1 p+ n+ p+ p+ n+ n+ n-well p-substrate (bulk) ELEC5970-001/6970-001 Lecture 4

  15. Leakage Reduction by Body Bias VBBp VDD o output input GND VBBn SiO2 Polysilicon (input) VBBn VBBp VDD output GND metal 1 p+ n+ p+ p+ n+ n+ n-well p-substrate (bulk) ELEC5970-001/6970-001 Lecture 4

  16. Body Bias, VBBn Polysilicon gate SiO2 p-type body + + + + + + + + + + + - Depletion region 0 < Vg < Vt + + + + + + + + + + + + + + + + + + + + + + + + + + Vt is a function of: Dopant concentration Thickness of oxide Polysilicon gate SiO2 p-type body - - - - - - - - - - - - - - - - - - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ++ + + + + + Vg < 0 ELEC5970-001/6970-001 Lecture 4

  17. Further on Body Bias • Large body bias can increase gate leakage (IG) via tunneling through oxide. • Body bias is kept less than 0.5V. • For VDD = 1.8V: • VBBn = -0.4V • VBBp = 2.2V ELEC5970-001/6970-001 Lecture 4

  18. Summary • Device scaling down reduces supply voltage • Reduced power • Increases delay • Optimum power-delay product by scaling down threshold voltage • Threshold voltage reduction increases subthreshold leakage power • Use body bias to reduce subthreshold leakage • Body bias may increase gate leakage ELEC5970-001/6970-001 Lecture 4

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