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Memory and I/O Subsystems

This overview delves into the intricacies of memory and I/O subsystems, emphasizing their hierarchy, various types, and vital components. Explore RAM types such as static and dynamic, as well as ROM designations and essential bus structures (data, address, and control). We’ll cover I/O interfacing techniques, including memory-mapped I/O and methods like programmed I/O, interrupt-driven I/O, and direct memory access (DMA). This engaging guide clarifies the interaction between memory and I/O devices, showcasing how they work cohesively within computer systems.

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Memory and I/O Subsystems

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  1. Memory and I/O Subsystems

  2. Memory Subsystems • Memory hierarchy • Memory types • RAM • Static • Dynamic • ROM • Size designations: “A x B” • A words of memory log2A address connections • B bits per word B data connections

  3. Input/Output CPU Memory 32 Data Bus System Bus 32 Address Bus Control Bus

  4. RAM Subsystem RAM Cells Address Decoder Memory,I/O Data Bus System Bus Address Bus Control Bus

  5. I/O Device Interfacing • Memory-Mapped I/O (most machines) • Similar bus interfacing for I/O and memory devices • Memory space includes I/O devices • Normal load/store instructions access I/O devices • Dedicated I/O (e.g. Intel CPUs) • A special control bus signal distinguishes memory accesses vs. accesses to I/O devices • Separate memory space and I/O space • Special in/out instructions access I/O devices

  6. I/O Interface Control I/O Device Status Data Address Decoder Data Bus System Bus Address Bus Control Bus

  7. I/O Methodologies • Programmed I/O (slowest) • CPU initiates all I/O operations. • CPU must repeatedly test device for data availability. • Interrupt-Driven I/O • I/O device signals that it has data available • Signalling is done through a system bus control signal (“interrupt request”). • CPU executes a special interrupt service routine to handle I/O • Requires hardware support (interrupt request arbitration) • Direct Memory Access (DMA) (fastest) • I/O system becomes the bus master and transfers data directly between memory and the I/O device. • CPU is “asleep” during the transfer. • Requires hardware support (interrupt system, DMA controller)

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