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Progress of SOI Pixel Detectors

Progress of SOI Pixel Detectors. Dec. 2, 2010 @ 量子ビーム X 線 Yasuo Arai, KEK yasuo.arai@kek.jp http://rd.kek.jp/project/soi/. OUTLINE. Overview of SOIPIX activities On-Going R&Ds Buried P-Well Wafer Thinning FZ-SOI Wafer Nested BNW/BPW Structure Double SOI Wafer Summary. SOI Pixel Detector.

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Progress of SOI Pixel Detectors

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  1. Progress of SOI Pixel Detectors Dec. 2, 2010 @量子ビームX線 Yasuo Arai, KEK yasuo.arai@kek.jp http://rd.kek.jp/project/soi/

  2. OUTLINE Overview of SOIPIX activities On-Going R&DsBuried P-WellWafer ThinningFZ-SOI WaferNested BNW/BPW StructureDouble SOI Wafer Summary

  3. SOI Pixel Detector Monolithic detector using Bonded wafer (SOI : Silicon-on-Insulator) of Hi-R and Low-R Si layers. • No mechanical bump bondings-> High Density, Low materialbudget-> Low parasitic Capacitance, High Sensitivity • Standard CMOS circuits can be built • Thin active Si layer (~40 nm)-> No Latch Up, Small SEE Cross section. • Based on Industrial standard technology • Seamless connection to Vertical Integration 3

  4. OKI 0.2 mm FD-SOI Pixel Process An example of a SOI Pixel cross section

  5. MPW (Multi Project Wafer) run ~Twice per Year

  6. Integration Type Pixel (INTPIX4) Largest Chip so far. 15 mm 10 mm 17x17 mm, 512x832 (~430k）pixels、13 Analog Out、CDS circuit in each pixel. 6

  7. Recent Process Improvements • Increase No. of Metal Layer : 4 -> 5 layers --> Better Power Grid and Higher Integration • Shrink MIM capacitor size : 1 -> 1.5 fF/um2 --> Smaller Pixel size become possible

  8. Recent Process Improvements • Relax drawing rule : 30o, 45o -> Circle --> Smooth field and Higher Break Down Voltage • Introduction of source-inserted body contacts --> Better body contacts (Less kink and history effects, Lower noise).

  9. On-Going R&Ds Back Gate Effect : Sensor voltage affect Transistor characteristics Buried P-Well (BPW) layer Wafer Thinning : Thin Sensor TAICO process Wafer Resistivity : Lower depletion voltage FZ SOI wafer Cross Talk : Reduce coupling between Sensor and Circuit Nested BNW/BPW Structure Radiation Hardness : Compensate traped charge Double SOI Wafer Higher Density: Increase pixel functionality.Vertical (3D) Integration

  10. a. Back Gate Effect Front Gate and Back Gate are coupled. (Back Gate Effect) Vg_back

  11. Buried p-Well (BPW) BPW Implantation Substrate Implantation Buried Oxide (BOX) SOI Si Pixel Peripheral P+ BPW • Cut Top Si and BOX • High Dose • Keep Top Si not affected • Low Dose • Suppress the back gate effect. • Shrink pixel size without loosing sensitive area. • Increase break down voltage with low dose region. • Less electric field in the BOX which may improve radiation hardness.

  12. Id-Vg and BPW w/o BPW with BPW=0V NMOS back channel open shift Back gate effect is suppressed by the BPW.

  13. b. Wafer Thinning :TAIKO process Back side process still can be done after thinning.

  14. Thinned to 110 umand diced I-V Characteristic Before & After Thinning No difference seen after thinning

  15. Infrared Laser (1064 nm) Response of Thinned Chip Full Depleted around 100V

  16. c. Wafer Resistivity : FZ SOI Wafer During the conventional SOI process, many slips were generated in the 8’’ FZ-SOI wafer. Slips We optimized the process parameters, and succeeded to perform the process without creating many slips.

  17. FZ-SOI Wafer Depletion Full Depleted @22V

  18. d. Nested BNW/BPW Structure implant • Signal is collected with the deep Buried P-well. • Back gate and Cross Talk are shielded with the Buried N-well. • Test chip is under process. Structure developed in cooperation between G. Deptuch (Fermilab) and I. Kurachi (OKISemi)

  19. Impurity Concentration

  20. e. Double SOI Layer wafer Increase radiation hardness by compensating Oxide/Interface Trap charge with middle layer bias. circuit additional conduction layer sensor Shield sensors from circuit

  21. Total Ionization Dose effect can be compensated by back bias Leak Current and VTh resumes to nearly original value by biasing back side even after 100Mrad. Vback= 0-10-20-30V 1015 p/cm2 (~100 Mrad) 1015 p/cm2 (~100 Mrad) beforeirradiation

  22. T-micro + OKI Semi + KEK/LBNL/Fermilab f. Vertical (3D) Integration Two chips are bonded with m-bump technology (~5 um pitch) of T-micro Co.

  23. Summary • Our SOI MPW run is operated regularly twice per year. • In addition to many chip designs, a lot of activities are going. • a. Buried P-Well technology is very successful to suppress the Back Gate problem. • b. Thinning to 110um by TAICO process works very well. • c. Wafer resistivity is greatly increased by using FZ-SOI wafer. • d. Nested BNW/BPW structure may resolve cross talk problem and opened possibility of new sensor structure. • e. Manufacturing of Double SOI wafer is being discussed with supply and processing companies. • f. 3D integration is also on-going.

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