5 Chapter

1. 5Chapter Synchronous Sequential Circuits

2. Logic Circuits- Review Logic Circuits Combinational Circuits Sequential Circuits • Employ storage elements in addition to logic gates. • Outputs are a function of the inputs and the state of the storage elements. • Output depend on present value of input + past input. • Consists of logic gates whose outputs are determined from the current combination of inputs. • Performs an operation that can be specified by a set of Boolean functions.

3. Overview • Storage Elements and Analysis • Introduction to sequential circuits • Types of sequential circuits • Storage elements • Latches • Flip-flops • Sequential circuit analysis • State tables • State diagrams

4. Outputs Inputs Combinational Logic Storage Elements Next State State Introduction to Sequential Circuits • A Sequential circuit contains: • Storage elements:Latches or Flip-Flops • Combinatorial Logic: • Implements a multiple-output switching function • Inputs are signals from the outside. • Outputs are signals to the outside. • Other inputs, State or Present State, are signals from storage elements. • The remaining outputs, Next State are inputs to storage elements.

5. Outputs Inputs Combina-tional Logic Storage Elements Next State State Introduction to Sequential Circuits • Sequential Logic • Output functionOutputs = g(Inputs, State) • Next state functionNext State = f(Inputs, State)

6. Types of Sequential Circuits • Depends on the times at which: • storage elements observe their inputs, and • storage elements change their state • Synchronous • Behavior defined from knowledge of its signals at discrete instances of time • Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) • Asynchronous • Behavior defined from knowledge of inputs at any instant of time and the order in continuous time in which inputs change • If clock just regarded as another input, all circuits are asynchronous!

7. X = X 5.3 Storage Elements :Latches • Storage elements • Maintain a binary state (0 or 1) indefinitely as long as power is delivered to the circuit • Switch states (01 or 10) when directed by an input signal • Most basic storage element • Used mainly to construct Flip-Flops • Asynchronous storage circuit • Types of latches: • SR Latches • S`R` Latches • D Latches

8. R (reset) Q Q S (set) S Q Q R Basic (NOR) S –R Latch • Cross-coupling two NOR gates gives theS – R Latch: Graphic Symbol

9. Basic (NOR) S –R Latch

10. Q Q Q R Basic (NAND) Ś –ŔLatch • “Cross-Coupling” two NAND gates gives the Ś -ŔLatch: Graphic Symbol S (set) Q S R (reset)

11. Basic (NAND)Ś –Ŕ Latch

12. S Q C S` Q 1 R 1 R` Clocked S - R Latch • Adding two NANDgates to the basicŚ - Ŕ NAND latchgives the clockedS – R latch: • Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high. • C means “control” or “clock”.

13. D Q C Q D Q Q C D Latch(Transparent Latch) • Adding an inverter to the S-R Latch,gives the D Latch: • Note that there are no “indeterminate”states!

14. Q D Q(t+1) 0 0 0 0 1 1 1 0 0 1 1 1 D Latch(Transparent Latch)

15. Chapter 5: Sequential Circuits 5.4: Flip-Flops

16. Flip-Flops • The latch timing problem • Master-slave flip-flop • Edge-triggered flip-flop • Other flip-flops - JK flip-flop - T flip-flop

17. The Latch Timing Problem • In a sequential circuit, paths may exist through combinational logic: • From one storage element to another • From a storage element back to the same storage element • The combinational logic between a latch output and a latch input may be as simple as an interconnect • For a clocked D-latch, the output Q depends on the input D whenever the clock input C has value 1

18. Y Clock Clock D Q Y Q C The Latch Timing Problem (continued) • Consider the following circuit: • Suppose that initially Y = 0. • As long as C = 1, the value of Y continues to change! • The changes are based on the delay present on the loop through the connection from Y back to Y. • This behavior is clearly unacceptable. • Desired behavior: Y changes only once per clock pulse

19. The Latch Timing Problem (continued) • A solution to the latch timing problem is to break the closed path from Y to Y within the storage element • The commonly-used, path-breaking solutions replace the clocked D-latch with: • a master-slave flip-flop • an edge-triggered flip-flop

20. D D D Q Q C C C Master-Slave Flip-Flop Master Slave Y • Consists of two clockedD latches in serieswith the clock on the second latch inverted • What happened when c=1? • The data from D input is transferred to the master . • The slave is disabled . • Any change in the input change the master output ( Y ) but can’t effect the slave output .

21. D D D Q Q C C C Master Slave Y • What happened when C=0? • The master is disabled . • The slave is enable. • The value of ( Y ) istransferred to the slave as input . • The output ( Q ) is equal ( Y ) . Conclusion: The output of the F.F. can change only during the transition of clock from 1 to 0 or atTrigger .

22. Timing

23. Timing • A trigger: The state of a latch or flip-flop is switched by a change of the control input.

24. Graphic Symbols

25. Graphic Symbols

26. Other flip-flops • Other F-Fs can be built using D F-F • There are four operation on a F-F- set to 1- Reset to 0- toggle ( complement ) of Q - nothing • There are tow F-F- JK F-F- T F-F

27. JK Flip-Flops

28. JK Flip-Flops D = JQ’ + K’Q

29. T Flip-Flops T Flip-Flops

30. T Flip-Flops

31. Characteristic Table

32. Characteristic Table

33. Characteristic Equations

35. State Equation

36. State Equation

39. Analysis • This circuit consist of : • 2 D F-F A and B • Input x • Output Y • Qt+1 = D • A= D A • B = D B

42. State Table

44. State Diagram

45. Input / output state

48. Analysis • 1 D F-F ( A ) • 2 Input X , Y • Qt+1 = D • D = A  X  y