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Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures

Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures. SAJID BALOCH. Prof. Dr. T. Arslan 1,2 Dr.Adrian Stoica 3. Supervisory Team. ACRONYMES. SEU (Single Event Effect) SET (Single Event Transient) SEB (Single Event Burnout)

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Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures

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  1. Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures SAJID BALOCH Prof. Dr. T. Arslan1,2 Dr.Adrian Stoica3 Supervisory Team

  2. ACRONYMES • SEU (Single Event Effect) • SET (Single Event Transient) • SEB (Single Event Burnout) • SEL (Single Event Latch-up) • Cfg (Configuration) • EDAC (Error Detection and Correction) • SoC (System on Chip) • FPGA (Field Programmable Gate Array) • DEU (Double Event Upset) • TEU (Triple Event Upset ) • MEU (Multiple Event Upsets)

  3. RECONFIGURABLE ARCHITECTURES a) FPGAs - SRAM - Anti Fuse - EPROM b) Reconfigurable SoC - General purpose - Domain Specific Re-Configurable SoC Architecture

  4. RADIATION EFFECTSRE-CONFIGURABLE ARCHITECTURES • PERMANANT FAULTS (due to SEL, SEB etc) • TEMPORARY FAULTS (due to SEU etc)

  5. SEU MITIGATION TECHNIQUES a) HARDWARE REDUNDANCY - Dual Modular Redundancy (DMR) - Triple Modular Redundancy (TMR) - EDAC Codes - Process Technology b) TIME REDUNDANCY c) COMBINATION (Hardware & Time)

  6. Radiation HardeningSEU EFFECTS • TRANSIENT FAULTS (Data Memory etc) • PERMANANT FAULTS (Cfg. Memory)

  7. SEU EFECTS Synchronous Circuits

  8. SEU EFECTS Configuration Memory

  9. SEU EFECTS ROUTING OF A SIGNAL

  10. Proposed SEU/SET MitigationTechnique based on: • Temporal Data Sampling • Weighted Voting Salient Features of The Proposed Technique: Auto Correction Mechanism for • 100% SEU Recovery • 100% Double Fault Recovery • Voter Faults Recovery

  11. Temporal Sampling Primary Section Secondary Section

  12. TEMPORAL SAMPLING Clock Scheme • 3 derivates of Main Clock • Each Clock is Phase shifted • 25% duty Cycle

  13. Minimized TermX4.X3.X0 + X5.X3.X0 + X5.X4.X0 + X4.X3.X1 + X5.X3.X1 + X5.X4.X1 + X4.X3.X2 + X5.X3.X2 + X5.X4.X2 + X5.X4.X3 + X3.X2.X1.X0 + X4.X2.X1.X0 + X5.X2.X1.X0 Weighted Voter Circuit

  14. SEU in Secondary Section Case Example

  15. Multiple Bit Upset Case Example

  16. Hardware Implementation of Proposed Scheme with Auto-Correction Mechanism

  17. Single Event Transition FaultData / Clock

  18. SEU/SET Simulator • SEU’s can be injected at instance • SEU of any duration can be injected • Multiple upsets can be injected

  19. Performance AnalysisFault Coverage

  20. Performance AnalysisArea Overhead Results are based on: 0.13µm CMOS technology

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