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ECE 659 Advanced VLSI Design Project Side-Channel Tolerant Logic Styles

Project Outline. The side-channel-attack tolerance becomes an extra design metric for embedded cryptosystems.To explore the design trade-off of different side-channel tolerant logic stylesDesign metrics: Power, performance, area, DPA tolerance, technology scaling downLogic styles: standard CMOS,

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ECE 659 Advanced VLSI Design Project Side-Channel Tolerant Logic Styles

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    1. ECE 659 Advanced VLSI Design Project Side-Channel Tolerant Logic Styles Lang Lin Sinan Hanay Tariq Bashir Ahmed Xiang Yun 5/9/2008

    2. Project Outline The side-channel-attack tolerance becomes an extra design metric for embedded cryptosystems. To explore the design trade-off of different side-channel tolerant logic styles Design metrics: Power, performance, area, DPA tolerance, technology scaling down Logic styles: standard CMOS, standard CMOS with all- NAND gates, SABL, MCML To learn the semi-custom design flow

    3. Semi-custom CMOS Design Flow

    4. Synthesis Flow using DC

    5. Synthesis of sbox5 using TSMC 180nm & vtvt 250nm synthesis library

    6. Layout of sbox5 using Synopsys Astro

    8. Using PERL script to extract HSPICE compatible netlist from RTL sbox5

    9. Power & Max Frequency Simulations on 2 CMOS implementations of sbox5

    10. SABL and MCML logic styles SABL Voltage-mode dynamic differential logic Precharge behavior prevents direct cascading gates: domino logic must be adopted. MCML Current-mode differential logic Low swing: both input and output are controlled to be 2.1V-2.5V for Vdd=2.5V Extra bias current source and bias voltage source

    11. Sbox Netlist for SPICE

    12. Why not a whole SABL/MCML DES?

    13. Power and Performance

    14. DPA tolerance DPA can work because of the power dependence on input patterns. Stronger power dependence = worse DPA tolerance

    15. How to improve DPA tolerance?

    16. How to improve DPA tolerance? (cont.)

    17. Quantification of DPA tolerance DPA procedure (classical) Give random input and generate transient power Make a key guess K1 and calculate the output Group the power waveforms based on a Selection Function Generate a DPA curve for K1 Try other keys and generate other DPA curves DPA curves: generated by Perl to handle the transient power waveforms Define a metric of DPA tolerance: quantify whether the correct key guess curve can be easily distinguished from other curves.

    18. Quantification of DPA tolerance (cont.)

    19. DPA tolerance R(t) R(t) is the ratio of three times standard deviation to the maximum power. R(t)>=1: the maximum power of the correct key guess curve is submerged by the wrong key guess curves. Thus, DPA cannot work or more power samples are required R(t)<1: a worse DPA tolerance

    20. Use different library to improve DPA tolerance DES SBOX implementations of different gate library may have different DPA tolerance. Case 1: mixed types of gate with various fan-ins Case 2: all 2-input NAND gates (better DPA tolerance)

    21. Technology scaling-down effects

    22. Layout Designs Work Done Standard Cell Library Guidelines Followed DRC checks has been done verified LVS checks has been done verified Parasitics Extraction has been done Different Layout Techniques has been compared Library Exchange Format (LEF)? A LEF file mainly consists of: Technology: layer, design rules, via definitions, metal capacitance Physical Design of Layout via Virtuoso Place and Route via Silicon Ensemble or Encounter

    23. Standard-cell based Layout Design Flow

    24. Layouts D-Flip Flop

    25. Layout Optimization

    26. Nor2 gate layout Area Reduction -> Diffusion Capacitance Reduction NOR2

    27. Layout Optimization 10% reduction in area, what about capacitance?

    28. AND 2 10% Reduction in Area

    29. Capacitance Extraction

    31. Area Estimation of sCMOS SBOX

    32. Example of SABL layout

    33. Example of MCML layout

    34. All the gates layout

    35. Area comparison of DES SBOX

    36. Encounter generated layout

    37. Steps for SABL layout generation Create the SABL Verilog synthesis file. Export the GDS files from Virtuoso. Create a valid technology file used for header generation. Use abstract to generate the LEF file. Encounter for layout generation.

    38. Area conclusion Semi-custom design. It is about 3 times larger for the SABL and MCML gates in terms of total cell area. For SABL logic, we made the assumption that the inverter drive takes about 10% of the cell area. The actual size of SABL and MCML might be larger due to the dual pins structure.

    39. Summary of comparison results

    40. DES Sbox5 under test

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