1 / 19

Understanding Interleaving Constraints in Shared-Memory Multi-Processor Systems

This article explores the complexities of parallel programming, emphasizing the difficulties in managing thread interleavings. It discusses the significance of synchronization mechanisms, such as semaphores and locks, in preventing concurrency bugs that arise from untested interleavings. The concept of Predecessor Set (PSet) is introduced as a solution to encode and enforce correct interleavings during program execution. Additionally, challenges surrounding the detection and management of data races, atomicity violations, and order violations are examined, shedding light on strategies to enhance program reliability and performance.

faxon
Télécharger la présentation

Understanding Interleaving Constraints in Shared-Memory Multi-Processor Systems

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. An Case for an Interleaving Constrained Shared-Memory Multi-Processor CS6260 Biao xiong, SrikanthBala.

  2. Why is Parallel Programming Hard? • Parallel programming is harder than single-threaded programming relatively easy? • Threads interleave in so many ways we can not decide the order of the execution of all the threads • some threads remain untested impossible to test all the interleavings.

  3. Why is Parallel Programming Hard? Legal Thread Interleavings Untested interleavings - cause for concurrency bugs Incorrect interleavings found during testing

  4. Solution • Synchronization operation: semaphores locks condition variable transaction. • Memeoryconsistancy model it reduces the number of legal thread interleavings. • Using PSet to test correct interleavings in program’s execution. • Avoid untested interleavings occur infrequently.

  5. Challenges • How to encode tested interleavings in a program’s binary? • Predecessor Set (PSet) interleaving constraints • How to efficiently enforce interleaving constraints at runtime? • Detect violations of PSetconstraints • Avoid violations by stalling or using rollback-and-re-execution support

  6. Constraining Interleavings • A majority of the concurrency bugs are avoidable • Data races, atomicity violations, and also order violations • Performance overhead is low • Untested interleavings in well-tested programs are likely to manifest rarely

  7. Data Race • A pair of memory accesses to the same memory location, at least one is write, neither one happens before the other

  8. Data race detectors • Happens-before Only data race in a given program execution • Lockset-based Predict data races. Not occur in a program’s execution.

  9. Benign data race • Not all data races are harmful data races, programmers allow data races to optimize performance.

  10. Atomicity Violation • Atomicity is a guarantee of isolation from cuncurrent processes x++? moveax,dwordptr [x] add eax,1 movdwordptr [x],eax

  11. Atomicity Violation Detectors • AVIO Analyse atomic region and detect atomicity violations.

  12. Order violation • Thread should be invoked only after thread2 executes the wait().

  13. Deterministic Multi-threading • Any execution of a multi-threaded program would yield the same output as long as the input remains the same.

  14. PSet • Defined for each static memory operation. • Consider true(read after write) as well as false(write after write and write after read)

  15. PSet • P in PSet of M iff 1.either P or M should be a write 2. P, M executed in two different threads (T1, T2) 3.M was immediately dependent on P 4. neither T1 nor T2 executed a read or a write between P and M.

  16. PSet • Example

  17. PSet • It can capture the fact that a benign data race interleaving is a correct interleaving, it will not hurt the performance.

  18. PSet • Instruction with Pset information for a 32-bit ISA

  19. Thank You

More Related