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Digital Beam Former Coefficient Management Using Advanced Embedded Processor Technology

Digital Beam Former Coefficient Management Using Advanced Embedded Processor Technology. High Performance Embedded Computing Workshop 18-20 September 2007. J Ryan Kenny Argy Krikelis Altera Corporation 101 Innovation Drive San Jose, CA 95134. Typical Beamforming Scenario.

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Digital Beam Former Coefficient Management Using Advanced Embedded Processor Technology

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  1. Digital Beam Former Coefficient Management Using Advanced Embedded Processor Technology High Performance Embedded Computing Workshop 18-20 September 2007 J Ryan Kenny Argy Krikelis Altera Corporation 101 Innovation Drive San Jose, CA 95134

  2. Typical Beamforming Scenario Front-End Processing (DDC – LPF – Equalisation) Adaptive Weight Computation Adaptive Beamforming Weight Computation (QR decomposition) Weight Computation (QR decomposition) Front-End Processing (DDC – LPF – Equalisation) Weight Computation (QR decomposition) Weight Computation (QR decomposition) Front-End Processing (DDC – LPF – Equalisation) Weight Computation (QR decomposition) Weight Computation (QR decomposition) Front-End Processing (DDC – LPF – Equalisation)

  3. PicaRisc Beamforming Architectural Solution Task Processing Unit (TPU) Data Out Data In Task & Event Busses Front-End Event Block #1 Front-End Event Block #2 QR Decomposition Event Block #1 QR Decomposition Event Block #2 QR Decomposition Event Block #3 Adaptive Beamforming Event Block #1 Adaptive Beamforming Event Block #2 Host i/f Configuration Bus Internal/External RAM • PicaRisc Architecture is a Multi-Thread Soft Processor • Intended to assume tasks of general purpose processor (less heat, less power) • Reduces bottlenecks normally found with embedded RISC processors • Routes and executes DSP subroutines • PicaRisc tools include • Compiler, Assembly Support, and Debug GUI

  4. Using PicaRisc in Radar Processing Scalable in two ways: multiple Task Processing Units, and multiple data flows • PicaRisc has been implemented in non-military products: • Communications infrastructure (packet routing, header processing) • Imaging, image processing (scalable bandwidth) • Can be targeted to Hard CopyTM Structured ASIC device • PicaRisc implementation and performance has been benchmarked at: • 200-400 MHz in several 90 nm FPGA parts • Roughly 700 Logic Elements for PicaRisc, and 400 per Task Processing Unit • STILL highly confidential technology – contact Altera for details under NDA

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