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High Speed Fully Integrated On-Chip DC/DC Power Converter

High Speed Fully Integrated On-Chip DC/DC Power Converter. Advisor Dr. Herbert Hess. By Prabal Upadhyaya upad4516@uidaho.edu. Sponsor: National Aeronautics and Space Administration (NASA). Microelectronics Research and Communications Institute (MRCI) University of Idaho

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High Speed Fully Integrated On-Chip DC/DC Power Converter

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  1. High Speed Fully Integrated On-Chip DC/DC Power Converter Advisor Dr. Herbert Hess By Prabal Upadhyaya upad4516@uidaho.edu Sponsor: National Aeronautics and Space Administration (NASA) Microelectronics Research and Communications Institute (MRCI) University of Idaho February 8, 2007

  2. Outline • Overview • Design of the High Speed DC/DC Power Converter • Simulation Results • Layout • Measured Results • Planned Future Work • Conclusion

  3. Overview • Last 15 years has seen a significant reduction in size of portable electronics devices

  4. Overview • Portable system is a collection of various sub-systems • Sub-systems may demand multiple input voltages and variable currents

  5. Overview • On-chip fully integrated DC/DC power converters that provides point of use power conversion can be a possible solution

  6. Overview • All switch-mode power converters use inductor • In the past, most DC/DC power converter were operated at low frequency and with discrete off chip inductor • Quality factor (Q) of an inductor is the function of frequency • higher Q can be achieved at high frequency Q f

  7. Overview • Benefits with high frequency switching • Integrated solution for the power converter • Reduced passive size • Higher Q inductor available

  8. Overview • Challenges with high frequency design • Parasitic capacitance • Power dissipation • Noise • Attenuation

  9. Design of the High Speed DC/DC Power Converter

  10. Sub-Components • Sub-components used in the power converter are • A Buck Converter • Two Comparators • A Voltage Control Oscillator (VCO) • A Charge Pump

  11. Block Diagram 3.3V 0V V <1.5V 1 0 1.5V t

  12. Buck Converter

  13. Comparator Buffer stage Amplification stage Decision making Stage

  14. Ring VCO

  15. Charge Pump – Cadence View

  16. Simulation Results Cadence Spectre

  17. Simulation Results • Output Voltage waveform has two kinds of output ripples • High frequency ripple due to switching at 1 GHz • Low frequency rippledue to control loopat 26 MHz Output Voltage = 1.5 V

  18. Simulation Results • High frequency ripple is 19 mV • Low frequency ripple is 65mV Output waveform

  19. Simulation Results • Vout changes with a change in the loading condition, but it takes less than 48 ns for the control loop to restore the output to the required voltage level Vout with variable load

  20. Simulation Results • Comparator produces logic 1 and 0 depending upon the output of the buck converter Comparator Out

  21. Simulation Results • Logic 1 or 0 from the comparator controls the operation of charge pump. • Logic 1 charges the capacitor • Logic 0 discharges the capacitor Charge Pump Out

  22. Simulation Results • VCO produces a near triangular wave of 1.02 GHz VCO Out

  23. Simulation Results • Duty-cycle of the PULSE driving the buck converter switch is altered based upon the near DC charge pump output voltage • Basic operation is to shift the DC level of the VCO signal to change the Duty-cycle of the PULSE PWM

  24. Simulation Results • Buck converter can supply upto 20mA of peak current. Iout

  25. Simulation Results • Power converter has output range of 1.0 V to 1.8 V, but limited to loading conditions • Peak current of 20mA can be drawn only in the range of 1.0 V to 1.8 V • Output voltage range is limited by duty-cycle and comparator Vo=1.1 V Vo=1.3 V Vo=1.4 V Vo=1.5 V Vo=1.8 V

  26. Simulation Results • Control loop created different duty cycles to adjust converter output Vo=1.1 V Vo=1.3 V Vo=1.5 V Vo=1.8 V PULSE with variable duty cycles

  27. Power Converter Layout

  28. Size 1180u x 900u Layout NMOS Closeloop – Cadence View Picture of a Fabricated Chip - NMOS CONTROL CIRCUIT INDUCTOR CAPACITOR BANK

  29. Size 1180u x 900u Layout PMOS Closeloop– Cadence View Picture of a Fabricated Chip - PMOS

  30. Measured Results – Preliminary

  31. Planned Future Work • Increase the switching frequency to achieve • higher Q for inductor • smaller passives • Increase efficiency • Eliminate low frequency ripple • Use the concept over to manufacture power converters in the industrial basis

  32. Planned Future Work – Control Ripple

  33. Conclusion • Fully integrated DC/DC converter realized in silicon • The converter takes 3.3V supply and can successfully realize voltage from 1.0 V to 1.8 V while supplying up to 20 mA of current • Diameter of the power converter is 1180u x 900u

  34. High Speed Fully Integrated On-Chip DC/DC Power Converter Thank You! Acknowledgements I would like to express my deep gratitude to Mr. Parag Upadhyaya, Washington State University Dr. Deukhyoun Heo, Washington State University And MRCI team For technical discussion and support University of Idaho February 8, 2007

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