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Exploring ART2GBT: ASIC Design and Hit Selection for High-Efficiency Data Formatting

This document provides insights into the ART2GBT ASIC developed by Sorin Martoiu at IFIN-HH, focusing on hit selection and data formatting processes. The study evaluates the performance of hit selection, proposing innovative methods such as the asynchronous smart token flag and cascaded priority encoders. Preliminary findings indicate a feasible design for 0.18 μm technology, optimal for low-range FPGAs like Spartan6 and Artix7. Key considerations include chip area, pad configuration, and power efficiency, along with a comprehensive overview of the proposed architecture.

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Exploring ART2GBT: ASIC Design and Hit Selection for High-Efficiency Data Formatting

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  1. Some thoughts on “ART2GBT” ASIC Sorin Martoiu, IFIN-HH

  2. De-serialize Data formatting Hit Selection

  3. De-serialize Hit Sel Data formatting

  4. De-serialize Hit Sel Data formatting

  5. How fast the hit selection can be? 1. (Asynchronous) Smart Token: FLAG_IN FLAG_IN FLAG_IN Token stops when SUM = MAX_HIT_LIST FLAG_IN 2. Cascaded Priority Encoders: FLAGS_IN

  6. How fast the hit selection can be? * MAX_HITS = 8 ** Very preliminary. 0.18 um tech MOSIS SCMOS (tsmc) (not IBM 0.13) / OSU FreePDK

  7. How big the ASIC can be? • Full layout (fast attempt, not fully tested, …) • De-serializers • Hit selection • Data formatting (simple mux with pass- transistors) • (very) crude estimation: • 700 x 700 um2 • No triplication (x4) • 0.18 -> 0.13 (x 0.7) • tech, std. cells, pads…

  8. How big the ASIC can be? • Number of I/O pads: • Inputs: 32 x 2 • Outputs: 40 x 2 • Total: 144 + pwr, clk, … • Options: • Reduce GBT i/f • 10 elinks@320MHz • Staggered pads • C4 ball bonds

  9. 5-bit Chip ID: max hits = 7 (80 bits = 7x11 + 3 spare) DOUT[39:0] A5 – 5+6 bits A12 – 5+6 bits BCID/ART A2 – 5+6 bits DOUT[79:40] empty empty BCID/ART A16 – 5+6 bits “000....00000” “000....00000” VMM 0, STRIP 0 ambiguity 32-bit Hit List: max hits = 8 (80 = 8x6 + 32) 32-bit hit list 12 2 5 16 DOUT[39:0] BCID/ART B.. DOUT[79:40] ART-6bits ..CID/ART ART-6bits ART-6bits ART-6bits empty

  10. Preliminary Conclusions • Hit selection can be done in 0.5 BC, possibly even less (FPGA and ASIC) • Design fits well in low-range FPGAs (SPARTAN6 or ARTIX7 – probably valid for Altera devices too) • ASIC implementation looks feasible in <0.18um tech • Final chip area is governed by the number of pads/packaging solution • Power?

  11. Spare Slides

  12. BCID transmission Cavern USA15 Fixed Latency GBT (TX) GBT (RX) TRIGGER PROC ART2GBT/VMM 3 1 2 3 1 2 BCID counter BCID counter TTC SYSTEM

  13. 8 hits 8 hits 4+4 hits 4+4 hits 2 of 4 traces partially lost 1 of 4 trace lost 2 of 8 trace lost Drift gap timing variation turned off…

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