1 / 14

COMPARISION OF INSTRUCTION SET ENCODINGS IN A SUPERSCALAR ARCHITECTURE by

COMPARISION OF INSTRUCTION SET ENCODINGS IN A SUPERSCALAR ARCHITECTURE by Piotr Nowak( 1817-1730) Sandeep Anand(1591-1971) Hemanth B Kunapuli(6125-5439) Subramanian Sankaran (3932-8457). METHODOLOGY:.

gerodi
Télécharger la présentation

COMPARISION OF INSTRUCTION SET ENCODINGS IN A SUPERSCALAR ARCHITECTURE by

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. COMPARISION OF INSTRUCTION SET ENCODINGS IN A SUPERSCALAR ARCHITECTURE by Piotr Nowak( 1817-1730) Sandeep Anand(1591-1971) Hemanth B Kunapuli(6125-5439) Subramanian Sankaran(3932-8457)

  2. METHODOLOGY: • We have implemented a simple superscalar ISS, using a simple design based on parallel 5 stage pipelines • We use the Simulator to compare two Instruction sets, one similar to the MIPS format containing 32 bits and the other a compressed encoding format having 16 bits. • We measured the relative performance using parameters like code size, IM bandwidth, overall execution time and the CPI • The multiple pipeline Simulator reveals limitations in the available ILP for the 16 bit compressed encoding.

  3. PIPELINE STRUCTURE

  4. Instruction Sets (16 bit and 32 bit versions)

  5. Instruction Sets (contd….)

  6. Results: • We had tested the optimized version of our ISS on 7 test benches, namely gcd.asm, mult.asm, memmove.asm, array.asm, matrix.asm and 2 custom test benches fir.asm and fft.asm • The CPI was plotted for all the benchmarks while utilizing different no of pipelines in the 16 bit and the 32 bit versions of the Instruction Set. • The total number of clock cycles, the bandwidth, and the Code size in bytes for each test bench was also plotted for the both the 16 bit and the 32 bit versions of the Instruction Set.

  7. Interpretation of the Results: • The CPI values for the 32 bit version improve by 27 % on an average when moving from 1 to 2 pipelines. Moving to more Pipelines doesn’t make any significant difference in the CPI value. • The CPI values for the 16 bit version improve by 22 % on an average when moving from 1 to 2 pipelines. Moving to more Pipelines doesn’t make any significant difference in the CPI value. • The no of clock cycles remains almost the same when moving from 16 to 32 bit versions of the Instruction Set. • The 16 bit Instruction set requires 23 % lesser bandwidth than the 32 bit version on an average. • The average code size in bytes for the 16 bit Instruction set is 28 % smaller then the 32 bit version Instruction set.

  8. Conclusion: • A Superscalar Architecture was used to compare 2 Instruction Sets. One, similar to the MIPS format with 32 bits and the other, a compressed 16 bit encoding • The compressed and the MIPS format benchmarks had nearly equal performance in the two issue Simulator. • The compressed format had significantly reduced Code size and the IM bandwidth. • The compressed format might perform better if cache misses were taken into account.

  9. References: • J. Circello and F. Goodrich, “ The Motorola 68060 Microprocessor,” • Proc. Compcon, IEEE Computer Society Press, Los Alamitos, Calif., 1993, pp. 73-78. • J. Hennessy and D. Patterson, “Computer Architecture, A quantitative Approach”, Morgan Kaufmann, San Mateo, Calif, 1990. • ShigezumiMatui, Mituyoshi Yamamoto et al., GMICRO/500 Microprocessor: Pipeline Structure of Superscalar Architecture, Central Research Laboratory, Hitachi, Ltd, Hitachi Microcomputer System Ltd. • Heui Lee, Paul Becket, Bill Appelbe, "High-Performance Extendable Instruction Set Computing," austcsac, pp.89, 6th Australasian Computer Systems Architecture Conference (AustCSAC'01), 2001 • Hasegawa, A.; Kawasaki, I.; Yamada, K.; Yoshioka, S.; Kawasaki, S.; Biswas, P.; “SH3: high code density, low power”, Micro, IEEE Volume 15, Issue 6, Dec. 1995 Pages:11 - 19

More Related