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Implementing Noise Cancellation Algorithm: Project Overview and Current Status

This document provides an overview of the progress on the Noise Cancellation Algorithm project as of February 28, 2005. It details the functional block layout and floorplan considerations. The overall project objective is to integrate the noise cancellation algorithm into hardware, with key milestones achieved including design and architecture proposals, and gate-level design completed. Current tasks involve finishing layouts, SPICE simulations, and making decisions on transistors and multipliers. Challenges include ensuring signal strength and optimizing design for performance.

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Implementing Noise Cancellation Algorithm: Project Overview and Current Status

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  1. Feb 28th, 2005 Functional Block Layout/Floorplan Noise Canceling in 1-D Data: Presentation #7 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Project Manager: Bobby Colyer Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

  2. Status • Design proposal (Done) • Architecture proposal (Done) • Size Estimates and Floorplan (Done) • Gate Level Design - Schematics (Done) • To be done: • Layout (35%) • Spice simulation

  3. Design Decisions • Successfully implemented Wallace + Booth • Changed register design

  4. Last week...

  5. Updated Floorplan

  6. Floating Point Adder (Vertical)

  7. Floating Point Adder (Horizontal)

  8. Wallace Tree (Before)

  9. Wallace Tree + Booth Encoding

  10. Barrel Shifter

  11. Comparator

  12. Add/Sub (FP Adder)

  13. Register (16 bit)

  14. Counter

  15. Timing (FPA) • Rise Time: • 65 picoseconds(10%-90%) • Fall Time: • 56 ps

  16. Updated Transistor Count

  17. Challenges… • Finishing up layout • Make sure that the signal strength is sufficient • Need to decide (multiplier) – symmetry vs. trans count

  18. Questions?

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