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Advanced Switch Design Principles for Tandem-Banyan Networks

This chapter discusses the design principles for advanced switching in telecom networks, focusing on tandem-Banyan networks, state-transition diagrams, routing algorithms, deflection error correction, and finite-state machine representation.

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Advanced Switch Design Principles for Tandem-Banyan Networks

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  1. IEG4020 Telecommunication Switching and Network Systems Chapter 5 Advanced Switch Design Principles

  2. Fig. 5.1. The tandem-banyan network. Packet filter for marked packets 1st Banyan Network 2nd Banyan Network KthBanyan Network Packet filter for unmarked packets mux mux Output 1 Output N 2

  3. Fig. 5.2. Relationship between the offered load k, carried load ck+1, and rejected load k+1 of the (k+1)th Banyan network in a tandem-Banyan network. (k+1)th Banyan Network (k+2)th Banyan Network k+1 k ck+1 MUX k= k+1+ck+1 3

  4. Analysis of Tandem Banyan Networks Let be the probability that a packet still fails to reach its destination after traveling through k Banyan networks. Note that . 4

  5. Fig. 5.3. The state-transition diagram of tandem-banyan network. 0 2n-1 2n-2 n+j+1 n+1 n j 1 5

  6. Fig. 5.4. The state-transition diagram of tandem-banyan network. 0 n n-1 j 1 6

  7. Fig. 5.5. Algebraic operations of shuffle and exchange. Perfect Shuffle Perfect Shuffle + Exchange 000 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 Packet on link x3x2x1-> x2x1d3 d3 = routing bit Packet on link x3x2x1-> x2 x1x3 7

  8. Fig. 5.6. Routing in shuffle-exchange network. ith bit of destination address used for routing at ith stage. 101 00 00 00 101 101 01 01 01 10 10 10 101 11 11 11 Sliding window routing: packet with source-destination label sn…sn-i…s1dn…dn-i+1…d1 occupies linksn-i…s1dn…dn-i+1…d1after stage i. 8

  9. Fig. 5.7. A shuffle-exchange network with n =3 and L =5. Bypass Packet B 100 Packet A 101 000 000 00 00 00 00 00 001 100 001 010 101 010 101 01 01 01 01 01 011 011 100 100 100 100 100 10 10 10 10 10 101 101 101 101 110 110 100 111 11 11 11 11 11 111 100 A reaches destination B deflected 100 100 100 100 100 Routing bit used by B at each stage 9

  10. Fig. 5.8. A 4-node feedback shuffle network. 0 00 1 0 01 1 0 10 1 0 11 1 10

  11. Node and Link Labels in Feedback Network xn … x10 xn … x1 xn … x11 xn-1…x11xn xn-1 … x11 S = sn … s1--> sn-1 … s1dn ---> sn-2 … s1dndn-1 … --> dn … d1= D 11

  12. Design issues in feedforward network L Ploss Design issues in feedback network Throughput 12

  13. Fig. 5.9. A node in the feedback shuffle network. Output Buffer Input Buffer 2x2 Deflection Switch Mechanism for removal and injection of packets One-packet buffer 13

  14. Ti= E[# additional steps | packet in state i] Ti=1+ pTi-1+qTn;1 in T0=0 Solving linear difference equations. Tn=(1-pn)/(pnq)  =link loading q =/4 , p =1 - /4   Analysis success prob. failure prob. 14

  15. Homogeneous solution to Ti= pTi-1is Ti= pi Particular solution to Ti - pTi-1=(1 + qTi) Substitute k(1 + qTn) = Ti yields k =1/(1-p)=1/q General Solution: Ti=(1+qTn)/q + cpi (c found by matching boundary condition T0=0) Analysis 15

  16. Little’s Law: Average delay x Throughput = Average backlog. Tn=2N =[8N(/4)2(1-/4)n]/[1-(1-/4)n] 8N(/4)(1- /4)n for large n e.g. Throughput per node =/N = 2(3/4)nfor = 1 Analysis [continue] 16

  17. Fig. 5.10. (a) Throughput as a function of link loading; (b) throughput as a function of offered load; for feedback shuffle-exchange network with n5. Throughput  Throughput  d/d < 0, unstable equilibrium max Unsaturated case max sat Saturated case sat ’ max Offered load 0 1 Link loading  sat max (a) (b) 17

  18. Fig. 5.11. A feedback bidirectional shuffle-exchange network 00 00 10 01 11 00 01 10 01 11 00 10 10 01 11 00 11 10 01 11 18

  19. Node traversed without deflections: If routing tag =1dn … 1d1 Sn … S1-->Sn-1 … S1dn-->Sn-2… S1dndn-1 … --> dn … d1 If routing tag =0dn … 0d1 Sn … S1-->d1Sn … S2-->d2d1Sn… S3 … --> dn … d1 Current state To output Next node xn ... x1 --------> xn-1 … x1r xn ... x1 --------> rxn … x2 1r 0r 19

  20. State diagram: n i+1 i 1 0 • Labeling of node outputs: 00 } Unshuffle links 01 Xn … X1 10 } Shuffle links 11 • Setting of routing tags: 0d10d2 … 0dn 1dn1dn-1 … 1d1 20

  21. Fig. 5.12. Illustration showing how a routing error can be corrected via a reverse link. Node sn-i-1 … s1dn … dn-i 1dn-1 Node sn-i … s1dn … dn-i+1 _ 1dn-1 Node sn-i-1 … s1dn … dn-i _ _ Packets deflected to node sn-i-1 … s1dn … dn-i can return to node sn-i … s1dn … dn-i+1 via this link. 21

  22. Fig. 5.13. The algorithm for correcting deflection errors. Packet at node xn…x1 with routing tag=ckrk…c1r1 Switched to output cr No Yes Remove two routing bits. New routing tag = ck-1rk-1 … c1r1 cr=ckrk? (undeflected) k=n? No Yes Add two routing bits: Reset routing tag to 0d1…0dn or 1dn…1d1 0xnif c=1 ck+1rk+1= { 1x1if c=0 New routing tag= ck+1rk+1ckrk…c1r1 Forward packet to next node 22

  23. Fig. 5.14. A state and its four adjacent states in the finite-state machine representation of packet state. 0xnckrk … c1r1xn-1 … x1rk _ _ 0xn 1rk _ 0rk 1x1 1x1ckrk … c1r1rkxn … x2 ckrk … c1r1xn … x1 1x1ckrk … c1r1rkxn … x2 _ 1x1 0rk 1rk 0xn ck-1rk-1 … c1r1xn-1 … x1rk regular transition Assume ck=1 deflection 23

  24. Fig. 5.15. Two possible packets-header implementations. Pointer Routing Tag Destination Address log n bits 2n bits n bits (a) Mode Regular Pointer Regular Routing Tag Error-Correction Pointer Error-Correction Routing Tag 1 bits log n bits 2n bits log n bits 2n bits (b) 24

  25. Fig. 5.16. The state-transition diagram of a packet in the bidirectional shuffle-exchange network in which the distance is the state. q p p p p i 1 0 n n-1 q q q q q = deflection probability 25

  26. T0=0 Ti=1+ pTi-1+ qTi+1 , 1  i  n -1 Tn=1+ pTn-1+ qTn Tn= n/(p-q) - [1/(p-q) - 1/p]  n/(p-q) p =1- (1-/4)4 = 4N/Tn max 1.469N/n [1-(p/q)n]  [1-(p/q)]  p  p  p  p Pr[Finding an undeflected packets at an output] = 1 - (1 - /4)4 = p Analysis 26

  27. 27 Define , we have ------(1) Particular solution to (1) Homogeneous solution to (1) 

  28. Fig. 5.17. A 4x4 banyan switch to be used in a node in the bidirectional shuffle-exchange network. 00 01 10 11 28

  29. Fig. 5.18. Illustration showing that both reverse links can be used to correct a deflection error. Bidirectional links a c b d In bidirectional shuffle-exchange network, node a and b connected to node d implies they are also connected to another common node c. 29

  30. 0 0 0 0 0 0 0 0 000 000 00 00 00 00 00 1 1 1 1 1 1 1 1 001 001 0 0 0 0 0 0 0 0 010 010 1 1 1 1 1 1 1 1 01 01 01 01 01 011 011 0 0 0 0 0 0 0 0 100 100 10 10 10 10 10 1 1 1 1 1 1 1 1 101 101 000 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 110 00 00 00 00 00 1 1 1 1 1 1 1 1 001 110 001 1 1 1 1 1 1 1 1 11 11 11 11 11 111 111 0 0 0 0 0 0 0 0 010 010 1 1 1 1 1 1 1 1 01 01 01 01 01 011 011 0 0 0 0 0 0 0 0 100 100 10 10 10 10 10 1 1 1 1 1 1 1 1 101 101 0 0 0 0 0 110 0 0 0 110 1 1 1 1 1 1 1 1 11 11 11 11 11 111 111 Fig. 5.19. (a) Fig. 5.19. (b) 30

  31. Fig. 5.19. Construction of a dual shuffle network using a shuffle-exchange and a unshuffle exchange networks: (a) Shuffle-exchange network, (b) unshuffle-exchange network, (c) dual shuffle-exchange network. 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 00 00 00 00 00 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 11 11 11 11 11 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 Unshuffle links (c) Shuffle links 31

  32. Dual Shuffle Network • N/2 nodes per stages, 2N links interconnect adjacent stages • Node label : xn … x2 • Global link label : • (1, xn … x1) for shuffle link. • (0, xn … x1) for unshuffle link. • Can be configured as • N x N switch ( treat (1, dn … d1) & (0, dn … d1) • as belonging to dn … d1) • or • 2N x 2N switch ( (1, dn … d1) belongs to 1dn … d1 • (0, dn … d1) belongs to 0dn … d1) 32

  33. Fig. 5.20. (a) DSN configured as N x N switch. (b) DSN configured as 2N x 2N switch. 1x2 router Multiplexer N x N SN N x N USN Output address space: dndn-1 ... d1;di{0,1} (a) 4x4 node interconnecting SN and USN N x N SN Output address space: 1dndn-1 … d1 N x N USN 2N inputs 2N outputs Output address space: 0dndn-1 … d1 (b) 33

  34. Fig. 5.21. An example of deflection error in the shuffle plane being corrected in the unshuffle plane. B reaches destination A reaches destination 000 000 00 00 00 00 00 001 001 010 010 01 01 01 01 01 011 011 000 000 10 10 10 10 10 001 001 010 010 11 11 11 11 11 011 011 Correcting error of A 000 000 00 00 00 00 00 001 001 010 010 01 01 01 01 01 011 011 000 000 10 10 10 10 10 001 001 010 010 11 11 11 11 11 011 011 Destination of A: 101 Destination of B: 100 packet A packet B 34

  35. Remove first-stage shuffle sn … s1( 1, sn … s2 dn)  … (1, dn … d1) Make sure packet reaches destination at node output rather than input at unshuffle network. * Set routing tag = (0d20d3 … 0dn0d1) sn … s1 (0, sn … s2d2)  (0, d2sn … s3d3) (0, di … d2sn … si+1di)  …  (0, dn-1… d2sndn)  (0, dndn-1 … d1) Further simplifications 35

  36. Fig. 5.22. (a) Block diagram of a switch node; (b) interconnection of bypass lines between adjacent switch nodes of same labels. Bypass line xn … x20 00 Postprocessor 00 4x4 Deflection switch xn … x21 01 01 Postprocessor 10 Postprocessor 10 11 11 Postprocessor Bypass line xn … x21 (a) xn … x2 xn … x2 (b) Bypass Lines 36

  37. Let be the conditional probability that a packet will reach its destination (or state 0) in k more steps given that its current state is i. 37

  38. It is a homogeneous linear difference equation in terms of i with boundary conditions. Substitute with The roots of the quadratic equation are The general solution of is 38

  39. By matching the boundary conditions at We can get the constants We can obtain a Chernoff bound on Ploss as follows: for some real z ≥ 1 39

  40. We are interested in Gn(z)for some real , to obtain a tight bound, must be sufficiently small, or z sufficiently large. We choose z large enough that S1(.) and S2(.) are both complex and express them in the polar coordinates of the complex plane as follows: 40

  41. When and Substitute this to the Chernoff bound on Ploss, we can get following result of complexity of DSN 41

  42. Fig. 5.23. Two random-walk models realizable with DSN: (a) random walk without boundary; (b) boundary with one-step reflection to the right. n+2 n+1 n i 1 0 Bypass location: n+2k; k=0,1,2... (a) n+1 n i 1 0 Transition probabilityfrom n+1to n=1 Bypass locations: n+2k; k=0,1,2... (b) 42

  43. Fig 5.24. Switching by loading packets from N inputs into RAM locations based on their targeted outputs and outputting packets into the N outputs in a round-robin fashion. Select inputs one by one RAM Partition 1 Inputs Outputs 1 1 Writes Reads N N Partition N B bits/s NB bits/s NB bits/s B bits/s 43

  44. Fig. 5.25. Buffer management in the shared-buffer memory switch. Pointer Packet H1 Packet 1 in List 1 Packet 2 in List 1 H T1 Packet 3 in List 1 If List iis empty, then both Tiand Hi point to the dummy address. T Dummy Packet Dummy Address indicating end of queue 44

  45. Switching using RAM ( compared to TSI in circuit switching) High speedup factor solved using parallelization ( multiple RAMs ) Shared or unshared buffer? Memory Switch 45

  46. Advantage Low loss prob. Superior to the extent that RAM is expensive. Disadvantage Does not solve congestion problem. May hide congestion problem No firewalls between different output queues. Shared buffer 46

  47. Linked list, (N+1 free list) H, T = Head and Tail of free List Hi, Ti= Head and Tail of List associated with output i. Write (H)  Packet load packet (Ti).NEXT  H add packet to list i Ti H update list i H  (H).NEXT update free list (Ti).NEXT  Dummy last entry of list i point to dummy address Buffer Management in shared-buffer Switch 47

  48. Read (T).NEXT  Hi return buffer to free list T Hi Hi  (Hi).NEXT update list i (T).NEXT  Dummy last entry of list i point to dummy address 48 ~END~

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