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Fault Detection by Examining Circuit Structure

Fault Detection by Examining Circuit Structure. Kaixiang You, Advisor: Kundan Nepal. Department of Electrical Engineering. Bucknell University, Lewisburg, PA. Background.

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Fault Detection by Examining Circuit Structure

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  1. Fault Detection by Examining Circuit Structure Kaixiang You, Advisor: Kundan Nepal Department of Electrical Engineering Bucknell University, Lewisburg, PA Background During the research we wrote some PERL (a computer language) scripts and used a software called FastScan to help us embed and analyze the implications. Results Stuck-at Faults: Path Delay Faults: A smaller number shows the fact that instead of adding all the implications, we will have less test patterns if we only add one implication to the circuit. What if we add certain amount of implications to the circuit? We did 5000 trials for s344 circuit. 1000 trials for 10% implications, 1000 trials for 20% implications, 1000 trials for 30% implications, 1000 trials for 40% implications and 1000 trials for 50% implications. If we rank all these 5000 trials, for the top 25 trials • Except circuit s349, the implications can increase the fault coverage • The implications could not decrease the number of untestable paths • The implications can reduce the number of test patterns • The implications could decrease the number of test patterns. However, in our research we discover that the number of test patterns is randomly generated. So far we didn’t find any obvious rules in it. • Future Work • . • Find the reason why sometimes fewer • Implications can reduce more test patterns • in path delay faults. • Analyze path delay faults by finding the • path delay time on each gate along the path. • Conclusions • For Path Delay Faults: • The implications can successfully decrease the number of test patterns and therefore reduce the testing time and testing cost. • The Implications couldn’t reduce the number of untestable paths. • Randomly generated implications sometimes can reduce even more test patterns, but the rules behind this phenomenon still need to be found. • For Stuck-at Faults: • The implications can increase the fault coverage (not every circuit) and therefore raise the testing efficiency. • The implications can reduce the number of test patterns and therefore lessen the testing time and testing cost.

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