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Figure 11.1 Fault detection in a simple circuit

a. w. 1. f. b. w. 2. w. d. 3. c. (a). Circuit. Fault. detected. Test. w. w. w. a /0. a /1. b /0. b /1. c /0. c /1. d /0. d /1. f. /0. f. /1. 1. 2. 3. 000. . . . 001. . . . . 010. . . . . 011. . . . . 100. . . 101. . .

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Figure 11.1 Fault detection in a simple circuit

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  1. a w 1 f b w 2 w d 3 c (a) Circuit Fault detected Test w w w a/0 a/1 b/0 b/1 c/0 c/1 d/0 d/1 f /0 f /1 1 2 3 000    001     010     011     100   101   110   111  (b) Faults detected by the various input valuations Figure 11.1 Fault detection in a simple circuit

  2. a w b 1 w = 1 2 c w = 0 3 f w = 1 4 Figure 11.2 A sensitized path

  3. w c 1 w 2 b d f w 3 w 4 Figure 11.3 Circuit for Example 11.1

  4. w 1 w 3 w 4 w 2 w f 3 w 4 w 1 w 2 w 3 Figure 11.5 Circuit with a tree structure

  5. Product term Test No. w w w w w w w w w w w w w 1 3 4 2 3 4 1 2 3 1 2 3 4 1 1 1 1 0 1 0 0 0 0 1 0 0 0 Stuck-at-0 2 0 1 0 1 1 1 1 1 0 0 1 0 1 tests 3 0 0 0 1 0 1 1 1 1 0 1 1 1 4 0 1 1 1 1 0 1 1 0 0 1 0 0 5 1 0 1 1 0 0 0 1 1 1 1 1 0 Stuck-at-1 6 1 1 0 0 1 1 0 0 0 1 0 0 1 tests 7 1 0 0 1 0 1 0 1 1 1 1 1 1 8 0 0 0 0 0 1 1 0 1 0 0 1 1 Figure 11.6 Derivation of tests for the circuit in Figure 11.5

  6. f w w f f f f f f f f f f f f f f f 11 1 2 0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 01 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Figure 11.7 All two-variable functions

  7. h b w d 1 f w 2 c k Figure 11.8 The XOR circuit

  8. Fault Circuit implements b/0 f = w 5 2 b/1 f = w 10 2 c/0 f = w 3 1 c/1 f = w 12 1 d/0 f = 0 0 d/1 f = w + w 7 1 2 h/0 f = 1 15 h/1 f = w w 4 1 2 k/0 f = 1 15 k/1 f = w w 2 1 2 Figure 11.9 The effect of various faults

  9. Percent faults detected Number of tests Figure 11.10 Effectiveness of random testing

  10. p x 0 0 Test Circuit Test vector under result generator test compressor x p n – 1 m – 1 Signature Figure 11.13 The testing arrangement

  11. f Q Q Q Q D D D D Q Q Q Q Clock x x x x 3 2 1 0 PRBS (a) Circuit x ··· 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1 3 x ··· 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 2 x ··· 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 1 x ··· 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 f ··· 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 (b) Generated sequence Figure 11.14 Pseudorandom binary sequence generator (PSRG)

  12. Signature Q Q Q Q D D D D p Q Q Q Q Clock Figure 11.15 Single-input compressor circuit

  13. Signature Q Q Q Q D D D D Q Q Q Q Clock p p p p 3 2 1 0 Figure 11.16 Multiple-input compressor circuit (MIC)

  14. Z-signature ¤ Normal Test MIC Z 0 W Combinational 1 X circuit y Y PRBSG-X Scan-out SIC Y-signature Flip-flops and multiplexers Scan-in PRBSG-y Figure 11.17 BIST in a sequential circuit

  15. Scan-out Combinational Combinational BILBO2 network BILBO1 network CN1 CN2 Scan-in Figure 11.19 Using BILBO circuits for testing

  16. w 1 w 2 f w 3 Figure P11.1 Circuit for problem 11.1

  17. w 1 w 2 f w 3 w 4 Figure P11.2 Circuit for problem 11.2

  18. w 1 w 2 f w 3 w 4 w 5 Figure P11.3 Circuit for problem 11.3

  19. w 1 w f 2 w 3 Figure P11.4 Circuit for problem 11.4

  20. w 4 w 3 w 2 p w 1 Figure P11.5 Circuit for problem 11.5

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