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TMS320 C6000

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hawa
9 diapositives · 344 Views · Sep 14, 2014

Instruction Set. TMS320 C6000. ADD .L1 A0, A1, A2. ADD .L2 -5 , B3, B4. ADD .L1 A2, A3, A5:A4. ADD .L1 A2, A5:A4 , A5:A4. ADD .L2 3 , B9:B8 , B9:B8. 'C 6xx Instruction Set - Operands. 'C 6xx Instruction Set - Cross Path. ADD .L 2x A 0, A 1, B 2

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TMS320 C6000
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  1. Instruction Set TMS320C6000

  2. ADD .L1 A0, A1, A2 ADD .L2 -5, B3, B4 ADD .L1 A2, A3, A5:A4 ADD .L1 A2, A5:A4, A5:A4 ADD .L2 3, B9:B8, B9:B8 'C6xxInstruction Set - Operands

  3. 'C6xxInstruction Set - Cross Path ADD .L2xA0,A1,B2 MPY .M1xA0,B6,A9 SUB .S1xA8,B2,A8 ADD .L1xA0,B0,A2 LDW .D1T2 *A0,B5 STW .D2T1A5,*B0

  4. 'C6xxInstruction SetParallel Operation L1 S1 M1 D1 L2 S2 M2 D2 ADD .L2xA0,A1,B2 | |MPY .M1xA0,B6,A9 SUB .S1xA8,B2,A8 ADD .L1xA0,B0,A2 LDW .D1T2 *A0,B5 || STW .D2T1A5,*B0

  5. Logical Arithmetic ANDCMPEQ (=)CMPGT (>)CMPLT (<)NOTORSHL (<<)SHR (>>)SSHLXOR ABSADDADDAADDKADD2MPYMPYHNEGSMPYSMPYHSADDSATSSUBSUBSUBASUBCSUB2ZERO Data Mgmt LDB/H/WMVMVCMVKMVKLMVKHMVKLHSTB/H/W Bit Mgmt Program Ctrl CLREXTLMBDNORMSET BIDLENOP Note: Refer to the 'C6000 CPU Reference Guide for more details. 'C62xInstruction Set (by category) Aritmetica di saturazione Se utilizzassi la classicaaritmetica di arrotondamentoquando, ad esempio in un procedimento di incremento di colore, giungessi al limite di rappresentazione di un dato un ulterioreincrementodeterminerebbe un overflow, con ilnumerocheraggiungerebbeerroneamenteillimiteopposto. Quandoiosommoinvece ad esempio due valori a 32 bitcheraggiungono un valoreeccedenteilimiti di rappresentazione, avreisemplicementebisogno di indicareche ho raggiuntoilvaloremassimorappresentabile. Questo è un eventoparticolarmentefrequente in applicazionimultimediali (ad esempioneivalori di coloredei pixel), in cui l’aritmetica di saturazione è appositamentepreposta. Two 16-Bit Integer Adds on Upper and Lower Register Halves if (cond) {((lsb16(src1) + lsb16(src2)) and FFFFh) or ((msb16(src1) + msb16(src2)) << 16) -> dst} else nop Integer Addition Using Addressing Mode Integer Addition Using Signed 16-Bit Constant Signed or Unsigned Integer Multiply 16 lsb x 16 lsb Signed or Unsigned Integer Multiply 16 msb x 16 msb Conditional Integer Subtract and Shift Used for Division if (cond) {if (src1 – src2 >= 0) ( (src1–src2) << 1) + 1 -> dst else src1 << 1 -> dst} else nop

  6. .L Unit .S Unit ABSADDANDCMPEQCMPGTCMPLTLMBDMVNEGNORM ADDADDKADD2ANDBCLREXTMVMVCMVKMVKLMVKH NOTORSADDSATSSUBSUBSUBCXORZERO MVKLHNEGNOT ORSETSHLSHRSSHLSUBSUB2XORZERO .D Unit ADDADDALDB/H/WMVNEG STB/H/WSUBSUBAZERO .M Unit MPYMPYH SMPYSMPYH Other NOP IDLE 'C62x Instruction Set (by unit) TMS320C62x/C64x/C67x Fixed-Point Instruction Set Note: Refer to the 'C6000 CPU Reference Guide for more details.

  7. .L Unit ABSADDANDCMPEQCMPGTCMPLTLMBDMVNEGNORM NOTORSADDSATSSUBSUBSUBCXORZERO ADDSPADDDPSUBSPSUBDPINTSPINTDPSPINTDPINTSPTRUNCDPTRUNCDPSP .S Unit ADDADDKADD2ANDBCLREXTMVMVCMVKMVKLMVKH NEGNOT ORSETSHLSHRSSHLSUBSUB2XORZERO ABSSPABSDPCMPGTSPCMPEQSPCMPLTSPCMPGTDPCMPEQDPCMPLTDPRCPSPRCPDPRSQRSPRSQRDPSPDP .M Unit MPYMPYHMPYLHMPYHL SMPYSMPYH MPYSPMPYDPMPYIMPYID 32-Bit Integer Multiply – Result Is Lower 32 Bits .D Unit ADDADDAB (B/H/W)ADDADLDB (B/H/W)LDDWMV NEGSTB (B/H/W) SUBSUBAB (B/H/W) ZERO No Unit Used NOP IDLE 32-Bit Integer Multiply – Result Is Lower 64 Bits Note: Refer to the 'C6000 CPU Reference Guide for more details. ' C67x: Superset of Floating-Point (by unit)

  8. Control Registers Interrupt Control Instruction Fetch Instruction Dispatch Emulation Advanced Instruction Packing AdvancedEmulation Instruction Decode Registers (A0 - A15) Registers (B0 - B15) Registers (A16 - A31) Registers (B16 - B31) L1 S1 M1 D1 D2 M2 S2 L2 + + X + + X + + x x + + + x + + x + + + x x + + X X + + x x + + ‘C62x: Dual 32-Bit Load/Store ‘C64x: Dual 64-Bit Load/Store ‘C67x: Dual 64-Bit Load/32-Bit Store Superset of Floating-Point

  9. Dual/Quad ArithABS2ADD2ADD4MAXMINSUB2SUB4SUBABS4 Bitwise LogicalANDN Shift & MergeSHLMBSHRMB Load ConstantMVK (5-bit) Data Pack/UnPACK2PACKH2PACKLH2PACKHL2PACKH4PACKL4UNPKHU4UNPKLU4SWAP2/4 Dual ArithmeticADD2SUB2 Bitwise LogicalANDANDNORXOR Address Calc.ADDAD Mem AccessLDDWLDNWLDNDWSTDWSTNWSTNDW Load ConstantMVK (5-bit) MultipliesMPYHIMPYLIMPYHIRMPYLIRMPY2SMPY2DOTP2DOTPN2DOTPRSU2DOTPNRSU2DOTPU4DOTPSU4GMPY4XPND2/4 Dual/Quad ArithSADD2SADDUS2SADD4 Bitwise LogicalANDN Shifts & MergeSHR2SHRU2SHLMBSHRMB Data Pack/UnPACK2PACKH2PACKLH2PACKHL2UNPKHU4UNPKLU4SWAP2SPACK2SPACKU4 ComparesCMPEQ2CMPEQ4CMPGT2CMPGT4 Branches/PCBDECBPOSBNOPADDKPC AverageAVG2AVG4 ShiftsROTLSSHVLSSHVR Bit OperationsBITC4BITRDEALSHFL MoveMVD 'C64x:Superset Fixed-Point of ‘C62x .S .L .D .M