1 / 21

Cadence Front to Back End Adil Sarwar

Cadence Front to Back End Adil Sarwar. March 2004. Presentation Overview. Tool Setup Virtuoso Schematic Editor (Composer) for design entry Analog Design Environment (Analog Artist) for netlisting and simulation. Virtuoso LE for layout Diva for physical Verification

hilaire
Télécharger la présentation

Cadence Front to Back End Adil Sarwar

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Cadence Front to Back EndAdil Sarwar March 2004

  2. Presentation Overview • Tool Setup • Virtuoso Schematic Editor (Composer) for design entry • Analog Design Environment (Analog Artist) for netlisting and simulation. • Virtuoso LE for layout • Diva for physical Verification • Mixed-signal simulations / AMS Designer

  3. Tool Setup • Source new cshrc file , IC 5.0 installed • Icfb –W -> to check the version of tool • cds.lib -> file in directory from where you want to run the tool • .cdsinit and .env files for initialization and bindkeys • icms , layoutPlus and icfb

  4. Cadence Flow Diagram Parasitic re-simulation Affirma Spectre Analog Simulator Virtuoso Schematic Editor back annotation Diva schematics Virtuoso XL Virtuoso Custom Router DRC LVS LPE Virtuoso Layout Editor Physical Design Physical Verification Stream PCell Libraries and technology files Rules files, technology files GDSII

  5. CIW Window

  6. Library Manager

  7. Creating Directories and cds.lib file

  8. Creating Schematic Cell

  9. Inverter Schematic

  10. CDF Parameters

  11. Adding Pins and Wire names

  12. Virtuoso – Cell Creation and LSW

  13. Virtuoso layout

  14. Inverter Layout

  15. Giving Terminal Names

  16. Diva DRC

  17. DRC Results in CIW Window

  18. LVS Setup

  19. LVS Results

  20. Model and Libraries • Models from NCSU Kit or From Mosis site • analogLib library was used for voltage sources and gnd • basic library was used for pins • dfII database and environment was used

  21. Tutorials and Useful sites • Tutorials available in Cadence Setup • Go to install directory, the tutorials should be here • <install_dir>/tools/dfII/samples/tutorials • cp –r cell_design ~/ • http://www.owlnet.rice.edu/~elec522/w9/virtuoso_layout/ • http://www.ee.princeton.edu/~cadence/usr/ • NCSU site for tarred kit

More Related