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Presented by: Reshef Schreiber Itay Leibovitz

Technion - Israel institute of technology department of Electrical Engineering. הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל. High speed digital systems laboratory. המעבדה למערכות ספרתיות מהירות. Serial Communication Board. Poster Part B. Presented by: Reshef Schreiber

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Presented by: Reshef Schreiber Itay Leibovitz

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  1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Serial Communication Board Poster Part B Presented by: Reshef Schreiber Itay Leibovitz Instructed by: Eran Segev Winter 2003

  2. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Abstract The Serial Communication Board (SCB) is a Mezzanine board which adds USB communication capability to the C6711 DSP Evaluation Board. A USB slave and host are implemented. The SCB itself is a daughter board that connects to the Evaluation board via the External Memory Interface (EMIF) connectors. The project (SCB) includes hardware and software. The hardware and the software demonstrate the ability of the TI 6711 DSP to communicate as a USB Slave and host controller. The hardware is based on a daughter board connected to the DSP evaluation board. The software includes drivers for both host and slave modes and enables data transfer from/to the DSP via a USB port.

  3. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Specification • Hardware: • TI DSP C6711 Evaluation Board • Altera FLEX EPF10K100 240 Pin FPGA • USB Host Controller – Philips ISP1362 • USB device controller DLP – USB245M • Software: • Serial Communication Board basic drivers for the Code Composer Studio • USB Host Controller Driver • USB test program for MS Windows

  4. D(0:15) USB Host Controller ISP1362 RD WR Data Data USB Device ADR(1:0) INT1 FPGA CS USB Device Controller BE0,BE1 USB_WR USB_WR ADR(6:0) Data Data USB_RD CS TXE RXF המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory System Block Diagram

  5. USB_CS USB_CS USB_RD USB_RD EAD EAD ( ( 6 6 : : 0 0 ) ) USB_WR USB_WR CE CE 2 2 Address Address BE BE 0 0 Decoder Decoder Select Select AWE AWE Reg_CS Reg_CS ARE ARE TXE TXE RXF RXF Test Test BOARD_ID BOARD_ID Data_Out Data_Out Reset_Out Reset_Out Register Register Mux Mux Sleep Sleep VCC_Out VCC_Out Data out Data out Data Bus Data Bus המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory FPGA Block Diagram Host CS

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