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IEEE 1284 I/O

IEEE 1284 I/O. IEEE 1284 Overview. Four parallel port interfaces through ENI 40 pins Uses external latching transceivers Host-side only No IEEE negotiation. Net+ARM/IEEE 1284 Signal Name Equivalencies. IEEE 1284 External Transceivers. Port Multiplexing to External Transceivers.

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IEEE 1284 I/O

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  1. IEEE 1284 I/O

  2. IEEE 1284 Overview • Four parallel port interfaces through ENI • 40 pins • Uses external latching transceivers • Host-side only • No IEEE negotiation

  3. Net+ARM/IEEE 1284 Signal Name Equivalencies

  4. IEEE 1284 External Transceivers

  5. Port Multiplexing to External Transceivers

  6. IEEE 1284 Modes

  7. Forward Compatibility Mode • Manual or Automatic mode • Selected by MAN bit in Port Control Register • Manual mode • STROBE* signal manually controlled by *MSTB • DATA signal driven by last byte to channel data register • Automatic mode • STROBE* and DATA automatically controlled based on BUSY • Slow or Fast mode • Selected by FAST in Port Control Register • DMA support provided

  8. Nibble Mode • Net+ARM asserts AUTOFD* (ready) • Peripheral puts first nibble on status line • Peripheral signals valid nibble via ACK* • Net+ARM deasserts AUTOFD* (busy) • Peripheral deasserts ACK* • Repeat for remaining nibbles

  9. Byte Mode • Net+ARM asserts AUTOFD* (ready) • Peripheral places first byte on DATA • Peripheral signals done by asserting ACK* • Net+ARM deasserts AUTOFD (busy) • Peripheral acknowledges by deasserting ACK • Net+ARM pulses STROBE* (via MSTB*) • Repeat for additional bytes

  10. Forward ECP Mode • Slow or Fast mode • Selected by FAST in Port Control Register • AUTOFD*, HSELECT*, and INIT* outputs are statically driven • Command vs. data encoding provided by AUTOFD*ACK*, BUSY, PE, PSELECT, and FAULT* are manually read via the port control register. • ACK* can be configured to generate an interrupt on a high-to-low transition • Net+ARM manipulates STROBE* and DATA signals based on the BUSY input • DMA support provided

  11. Reverse ECP Mode • HSELECT*, and INIT* statically driven based on bit settings in the port control registers. • STROBE* always high when in reverse ECP mode. • PE, PSELECT, and FAULT* are manually read via the port control register • Net+ARM automatically manipulates AUTOFD* based on ACK* • DATA bytes are stored in the channel data register. • When four bytes have been received, or the reverse ECP channel is “closed,” the inbound buffer ready (IBR) bit is set in the channel control register.

  12. Reverse ECP Mode (2) • When IBR is set, RXFDB shows the number of bytes available • IBR can be configured to generate an interrupt or used by DMA • BUSY provides the command/data • Reverse ECP mode provides a character timer that can be used to guard against stale data sitting in the port data register. • DMA support provided – see HW manual for details

  13. Forward/Reverse ECP mode transitions • Software action required • Forward ÞReverse • Assert INIT* • Assert BIDIR • Now in Forward mode • Reverse ÞForward • Deassert INIT • Wait for PE high • Deassert BIDIR • Now in Reverse mode

  14. EPP Mode • Net+ARM can read/write data or address in peripheral

  15. EPP Mode Data Write • Net+ARM issues DATA and STROBE* low to indicate a write cycle • AUTOFD* is asserted since BUSY is inactive • Net+ARM waits the peripheral to acknowledge via active BUSY • Net+ARM deasserts AUTOFD to acknowledge the peripheral • Net+ARM drives STROBE inactive and tri-states the DATA bus to end the EPP write cycle • The above is repeated as required

  16. EPP Data Read • NET+ARM deasserts STROBE* indicating a read cycle • AUTOFD* asserted since BUSY is inactive • Net+ARM waits for acknowledgment from the peripheral via active BUSY • Net+ARM deasserts AUTOFD* to acknowledge the peripheral; read data is latched • The peripheral removes BUSY and tri-states the data bus • The above is repeated as required

  17. EPP Address Write • Net+ARM executes a write cycle to the EPP address byte address in the port by setting DATA and STROBE* • HSELECT* is asserted since BUSY is inactive • Net+ARM waits for acknowledgment from the peripheral via active BUSY • Net+ARM deasserts HSELECT* to acknowledge the peripheral • Net+ARM drives STROBE* inactive and tri-states the DATA bus to end the EPP write cycle • The above is repeated as necessary

  18. EPP Address Read • Net+ARM deasserts STROBE* to indicate a read cycle • HSELECT* is asserted since BUSY is inactive • Net+ARM waits for the acknowledgment from the peripheral via active BUSY. The peripheral drives the data bus when BUSY is asserted • Net+ARM deasserts HSELECT* to acknowledge the peripheral; read data is latched at this time • The peripheral removes BUSY and tri-states the data bus • The above is repeated as required

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