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Digital Design: Sequential Logic Blocks

Digital Design: Sequential Logic Blocks. Credits : Slides adapted from: J.F. Wakerly, Digital Design , 4/e, Prentice Hall, 2006 C.H. Roth, Fundamentals of Logic Design , 5/e, Thomson, 2004 R.H. Katz, G. Borriello, Contemporary Logic Design , 2/e, Prentice-Hall, 2005. OUT1. OUT2. OUT3.

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Digital Design: Sequential Logic Blocks

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  1. Digital Design: Sequential Logic Blocks Credits: Slides adapted from: J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004 R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005

  2. OUT1 OUT2 OUT3 Clear Clr Clr Clr Clr D Q D Q D Q D Q CLK IN1 IN2 IN3 IN4 Registers • A collection of 2 or more D flip flops with a common clock • Registers are often used to store a collection of related bits (e.g. a byte of data in a computer) OUT4

  3. A “standard” 4-bit register IC

  4. A “standard” 8-bit register IC

  5. Registers with 3-state outputs (a) Symbol (b) Functional Diagram

  6. A “standard” 8-bit register with 3-state outputs

  7. 0 1 0 1 0 1 Out0 D Q CK D Q CK D Q CK In0 CE ClrN Out 8 8 Q ClrN Clr CE D Out1 In1 Load Clk In Out7 In7 Clk Registers with clock enable (a) Symbol

  8. A standard 8 bit register with clock enable (= “gated” clock)

  9. Registers application: Data Transfers

  10. block diagram Shift Registers • It is a register that stores input values in sequence. At each clock tick the values stored are shifted from one flip flop to the adjacent

  11. tFF1 < Tclock – Tsu2 + tskew Cascading Flip Flops Setup Constraint: Hold Constraint: tFF1 > Th2 + tskew • If flip flops were ideal (tFF = 0) shift registers would not work ! The hold time constraint would not be satisfied !! • For long shift registers, skew can easily become an issue and cause hold time constraint to be violated

  12. Shift Registers (cont’d)

  13. Shift Registers (cont’d)

  14. Shift registers (cont’d)

  15. clear sets the register contentsand output to 0s1 and s0 determine the shift function s0 s1 function 0 0 hold state 0 1 shift right 1 0 shift left 1 1 load new input output Universal Shift Register clear clock s0 s1 input Universal shift register • serial or parallel inputs • serial or parallel outputs • permits shift left or right • shift in new values from left or right right_out left_in left_out right_in

  16. Shift register application • Parallel-to-serial conversion for serial transmission parallel outputs parallel inputs Parallel-to-serial conversion Serial-to-parallel conversion serial transmission

  17. OUT OUT1 OUT2 OUT3 OUT4 CLR D Q D Q D Q D Q IN Shift register application (cont’d) • Pattern Recognizer • in this case, recognizing the pattern 1001 CLK

  18. NOTE: with 4 FF we make only 4 patterns OUT1 OUT2 OUT3 OUT4 START S R R R IN D Q D Q D Q D Q CLK Shift register application (cont’d) • Ring Counter • counters are systems that sequences through a fixed set of patterns • in this case the sequence is 1000, 0100, 0010, 0001 provided that one of the given patterns is forced as initial state (by loading or set/reset)

  19. OUT1 OUT2 OUT3 OUT4 IN D Q D Q D Q D Q CLK we can use 0000 or 1111 as reset state • Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 NOTE: with 4 FF we make 8 patterns. Adjacent patterns have distance one (glitch free decoding) Shift register application (cont’d) • Johnson (= Moebius = Twisted-ring) Counter • How does this counter work?

  20. Ring and Johnson counter Timings

  21. Binary Counters • A counter is a clocked sequential circuit that sequences through a fixed set of patterns • A counter with m-states is called a modulo-m-counter, or sometimes a divide-by-m counter • The most commonly used counter type is an n-bit binary counter (each of the states is encoded as the corresponding n-bit binary integer)

  22. Binary Counters (cont’d) • Ripple counters • Don’t use them !!! The output of the flip-flops are fed into the clock pin causing skew. As a result reliability becomes an issue (especially for high speed applications). • Synchronous counters • The operation of the flip flops is synchronized by a common clock.

  23. Synchronous Binary Counters

  24. Synchronous Binary Counters (cont’d)

  25. Sync. Binary Counters with T-FF QA toggles always (every clock tick) QB toggles every time QA = 1 QC toggles every time QA ANDQB are both 1

  26. OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q CLK "1" Sync. Binary Counters with D-FF • XOR decides when bit should be toggled • The toggling rule is as follows: always for low-order bit; only when first bit is true for second bit; only when first and second bit are true for third bit; and so on

  27. Example: Binary Up/Down Counter

  28. Binary Up/Down Counter (cont’d)

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