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Introduction to Sequential Logic Design

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16 diapositives · 310 Views · Aug 14, 2014

This introduction covers the fundamentals of latches and flip-flops, which are essential components of sequential circuits. A bistable memory device, such as a latch, is level-sensitive and continuously monitors its inputs, while a flip-flop is edge-triggered and responds only at specific clock signals. We explore the S-R latch, its behavior, timing parameters, and issues like metastability. The differences between S-R and D latches are also discussed, highlighting their applications in storing information without encountering simultaneous set/reset problems.

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Introduction to Sequential Logic Design
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  1. Introduction to Sequential Logic Design Latches

  2. Terminology • A bistable memory device is the generic term for the elements we are studying. • Latches and flip-flops (FFs) are the basic building blocks of sequential circuits. • latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal. • flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.

  3. S-R latch S sets the Q output to 1, R resets the Q output to 0. If both R, S are negated, the latch remains in the state that it was forced to (like a bistable element). QN is normally the complement of Q (but sometimes NOT).

  4. S-R latch operation

  5. Metastability is possibleif S and R are negatedsimultaneously. S-R latch operation

  6. S-R latch timing parameters • Propagation delay • Minimum pulse width

  7. S-R latch symbols

  8. S-R latch using NAND gates(S-bar-R-bar latch)

  9. S-R latch with enable

  10. S-R latch with enable

  11. S-R latch with enable

  12. D latch D Q C Q

  13. D-latch operation When C is asserted, Q follows the D input, the latch is “open” and the path (D-->Q) is “transparent”. When C is negated, the latch “closes” and Q retains its last value.

  14. D-latch timing parameters • Propagation delay (from C or D) • Setup time (D before C edge) • Hold time (D after C edge)

  15. S-R vs. D latches • S-R • Useful in control applications, “set” and “reset” • S=R=1 problem • Metastability problem when S, R are negated simultaneously, or a pulse applied to S, R is too short. • D • Store bits of information • No S=R=1 problem • Metastability still possible.

  16. Next… • Flip-flops • Read Ch-7.2