Introduction to Sequential Logic Design

Introduction to Sequential Logic Design Bistable elements Latches

Sequential Systems • A combinational system is a system whose outputs depends only upon its current inputs. • A sequential system is a system whose output depends on current input and past history of inputs. • All systems we have looked at to date have been combinational systems.

Sequential Circuits • Outputs depends on the current inputs and the system’s current state. • “State” embodies all the information about the past needed to predict current output based on current input. • State variables, one or more bits of information. The state is a collection of state variables whose values at any one time contain all the information about the past necessary to account for the circuit’s future behavior. Herbert Hellerman, Digital Computer Systems Principles

Describing Sequential Circuits • State table • For each current-state, specify next-states as function of inputs • For each current-state, specify outputs as function of inputs • State diagram • Graphical version of state table

Finite State Machine • A circuit with n binary state variables has 2n possible states, which is always finite, so sequential circuits are sometimes called Finite-State Machines(FSM). • For most sequential circuits, the state changes occur at times specified by a free-running clock signal. • Clock is active high: state changes occur ar rising edge • Clock is active low:falling edge

Clock signals • Very important with most sequential circuits • State variables change state at clock edge.

Feedback sequential circuit: using ordinary gates and feedback loops to obtain memory in a logic circuit, thus creating sequential circuit building blocks such as latches and FFs. • Clocked synchronous state machine: using these building blocks (edge-triggered D FFs) to create circuits.

HIGH LOW LOW HIGH LOW HIGH HIGH LOW Bistable element • The simplest sequential circuit, no way to control its state. • Two states • One state variable, say, Q, two possible states

2.0 V 2.0 V Analog analysis • Assume pure CMOS thresholds, 5V rail • Theoretical threshold center is 2.5 V 2.5 V 5.0 V 2.51 V 2.5 V 0.0 V 2.5 V 0.0 V 4.8 V 5.0 V 2.5 V

Metastability • Metastability is inherent in any bistable circuit • Two stable points, one metastable point

Another look at metastability

Why all the harping on metastability? • All real systems are subject to it • Problems are caused by “asynchronous inputs” that do not meet flip-flop setup and hold times. • Details in Chapter-7 flip-flop descriptions and in Section 8.9 (later in quarter). • Especially severe in high-speed systems • since clock periods are so short, “metastability resolution time” can be longer than one clock period. • Many digital designers, products, and companies have been burned by this phenomenom.

Back to the bistable…. • How to control it? • Screwdriver • Control inputs • S-R latch

Terminology • A bistable memory device is the generic term for the elements we are studying. • Latches and flip-flops(FFs) are the basic building blocks of sequential circuits. • latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal. • flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal. • Warning: some authors use the terminology Flip-Flop and Clocked Flip-Flop instead of latch and Flip-Flop • latch, flip-flop more standard

S-R latch S sets the Q output to 1, R resets the Q output to 0. If both R, S are negated, the latch remains in the state that it was forced to (like a bistable element). QN is normally the complement of Q (but sometimes NOT).

Metastability is possibleif S and R are negatedsimultaneously. S-R latch operation

S-R latch timing parameters • Propagation delay • Minimum pulse width

S-R latch symbols

S-R latch using NAND gates(S-bar-R-bar latch)

S-R latch with enable

D latch D Q C Q

D-latch operation When C is asserted, Q follows the D input, the latch is “open” and the path (D-->Q) is “transparent”. When C is negated, the latch “closes” and Q retains its last value.

D-latch timing parameters • Propagation delay (from C or D) • Setup time (D before C edge) • Hold time (D after C edge)

S-R vs D latches • S-R • Useful in control applications, “set” and “reset” • S=R=1 problem • Metastability problem when S, R are negated simultaneously, or a pulse applied to S, R is too short. • D • Store bits of information • No S=R=1 problem • Metability still possible.

Next… • HW #10 (Last homework…) • Flip-flops • Read Ch-7.2

Introduction to Sequential Logic Design

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