1 / 114

Introduction to Sequential Design

Introduction to Sequential Design. Types of Logic Circuits. Logic circuits can be: Combinational Logic Circuits-outputs depend only on current inputs Sequential Logic Circuits-outputs depends not only on current inputs but also on the past sequence of inputs. Sequential Circuit Models.

stone-graham
Télécharger la présentation

Introduction to Sequential Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Introduction to Sequential Design

  2. Types of Logic Circuits • Logic circuits can be: • Combinational Logic Circuits-outputs depend only on current inputs • Sequential Logic Circuits-outputs depends not only on current inputs but also on the past sequence of inputs

  3. Sequential Circuit Models

  4. Combinational Logic Delay Longest delay Shortest delay Longest timing delay = 5ns+5ns+5ns+5ns = 20ns Shortest timing delay = 5ns We will use the longest delay to represent the combinational logic (CL) delay, tcl

  5. Combinational Logic (CL) Cloud Model Tcl=20ns Tcl=20ns

  6. Memory

  7. Memory • We will add memory (or registers) to our logic circuits. This will allow us to design sequential circuits.

  8. Registers • We will represent registers with the following block diagram Clock and reset are control signals Ns and ps are data signals

  9. Sequential Systems Block Diagrams

  10. Sequential Systems General Block Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset CL= Combinational Logic Cloud Reg= D Registers

  11. Sequential SystemsGeneral Block Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset X is the input data vector Y is the output data vector

  12. Sequential SystemsBlock Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset Ns is the next state data vector Ps is the present state data vector

  13. Sequential SystemsBlock Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset Notice we have a feedback path which combines the ps data vector with the input vector to generate a new ns data vector.

  14. Sequential SystemsBlock Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset Mathematically, we say Or, ns is a function F of X and ps and Y is a function H of ps.

  15. F Logic Register Example Circuit Schematic ns ps X input H Logic (buffer) Block Diagram

  16. F Logic Register Example Circuit Schematic ns ps X input H Logic (buffer) State Equations

  17. Finite State Machine (FSM) General Models

  18. Moore FSM General Block Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset CL= Combinational Logic Cloud Reg= D Registers

  19. Moore FSM State Equations Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

  20. Mealy FSM Block Diagram and State Equations Next State Present State Input Vector Output Vector Feedback Path Output Y is also a function of input X

  21. Mealy-Moore FSM Block Diagram and State Equations Present State Next State Input Vector Mealy Outputs Moore Outputs

  22. State Diagrams

  23. State Bubble

  24. State Bubble Example Conditional Transition Unconditional Transition State name = S0 State value = 00 Y = 0 for this state We leave this state if upn=1, We remain in this state if upn=0

  25. Memory Devices

  26. Memory Devices • Data Latch (D-latch) • Flip-flops (edge triggered) • D-FF, D Register • JK-FF • T-FF

  27. D-FF Positive Edge TriggeredBlock Diagram Symbol 4 inputs: D,Clk,Pre,Rst One output: Q D = Data Input Clk = Clock Input Pre = Preset Input Rst = Reset Input

  28. D-FF Truth Table Symbol Truth Table Equation (rising clock)

  29. D-FF Truth Table Symbol Truth Table Equation (rising clock) Pre= Preset Input (active low) Rst = Reset Input (active low) Highest priority

  30. D-FF Truth Table Symbol Truth Table Equation (rising clock) D = Data Input Clk = Clock input Qn = Register Output

  31. FSM Examples

  32. Example– 2-bit Up Counter • State Diagram Clock is implied

  33. Example – 2-bit Up Counter • State Table State Value Assignment Let Output Vector Let S0 = reset state

  34. Example – 2-bit Up Counter • Truth Table

  35. Example – 2-bit Up Counter • Excitation Equations

  36. Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

  37. Reg Block F Logic Y Vector H Logic Logic Diagram No X Vector in this Example No H Logic needed

  38. Logic Diagram

  39. Flash Animation

  40. Example 3– 2-bit Down Counter • State Diagram Clock is implied

  41. Example – 2-bit Down Counter • State Table Let Let S0 = reset state

  42. Example – 2-bit Down Counter • Truth Table

  43. Example – 2-bit Down Counter • Excitation Equations

  44. Recall Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

  45. Logic Diagram Reg Block F Logic Y Vector H Logic No X Vector in this Example

  46. Logic Diagram

  47. Example 4 – 2-bit Up/Down Counter • State Diagram

  48. Example – 2-bit Up/Down Counter • State Diagram Shorthand Notation

  49. Example – 2-bit Up/Down Counter • State Table Let Let S0 = reset state

  50. Example – 2-bit Up/Down Counter • Truth Table

More Related