1 / 17

Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits

Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits. David Harris Harvey Mudd College Spring 2004. Outline. Floorplanning Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking. Sequencing. Combinational logic

gur
Télécharger la présentation

Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Introduction toCMOS VLSIDesignLecture 10: Sequential Circuits David Harris Harvey Mudd College Spring 2004

  2. Outline • Floorplanning • Sequencing • Sequencing Element Design • Max and Min-Delay • Clock Skew • Time Borrowing • Two-Phase Clocking 10: Sequential Circuits

  3. Sequencing • Combinational logic • output depends on current inputs • Sequential logic • output depends on current and previous inputs • Requires separating previous, current, future • Called state or tokens • Ex: FSM, pipeline 10: Sequential Circuits

  4. Sequencing Cont. • If tokens moved through pipeline at constant speed, no sequencing elements would be necessary • Ex: fiber-optic cable • Light pulses (tokens) are sent down cable • Next pulse sent before first reaches end of cable • No need for hardware to separate pulses • But dispersion sets min time between pulses • This is called wave pipelining in circuits • In most circuits, dispersion is high • Delay fast tokens so they don’t catch slow ones. 10: Sequential Circuits

  5. Sequencing Overhead • Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. • Inevitably adds some delay to the slow tokens • Makes circuit slower than just the logic delay • Called sequencing overhead • Some people call this clocking overhead • But it applies to asynchronous circuits too • Inevitable side effect of maintaining sequence 10: Sequential Circuits

  6. Pipelining 10: Sequential Circuits

  7. Sequencing Methods • Flip-flops • 2-Phase Latches • Pulsed Latches 10: Sequential Circuits

  8. Timing Diagrams Contamination and Propagation Delays 10: Sequential Circuits

  9. Max-Delay: Flip-Flops 10: Sequential Circuits

  10. Max-Delay: Flip-Flops 10: Sequential Circuits

  11. Min-Delay: Flip-Flops 10: Sequential Circuits

  12. Min-Delay: Flip-Flops 10: Sequential Circuits

  13. Positive Skew & Negative Skew PS Clk & Data Same Direction NS Clk & Data Difft Direction 10: Sequential Circuits

  14. Skew: Flip-Flops 10: Sequential Circuits

  15. Skew: Flip-Flops 10: Sequential Circuits

  16. Safe Flip-Flop • In class, use flip-flop with nonoverlapping clocks • Very slow – nonoverlap adds to setup time • But no hold times • In industry, use a better timing analyzer • Add buffers to slow signals if hold time is at risk 10: Sequential Circuits

  17. Summary • Flip-Flops: • Very easy to use, supported by all tools • 2-Phase Transparent Latches: • Lots of skew tolerance and time borrowing • Pulsed Latches: • Fast, some skew tol & borrow, hold time risk 10: Sequential Circuits

More Related