Future Si Vertex Detector Readout System Proposal for SVD-3 Upgrade

1. Electronics/DAQ for SVD2+SVD3 Electronics/DAQ for SVD2+SVD3 HL6 @ KEK, 17 Nov 2004 We want toinvestigatepenguins! Manfred Pernicka, HEPHY Vienna

2. Proposal for the readout system of the future Si. Vertex Detector for BELLE • ADCclock: Clock phase can be adjusted for every input channel. • Each channel has its own signal processing, needs the same time to process its data. The data could be final or would need a final processing.Complete pipeline, no dead time • Fast event data block output, up to 80 MHZ • Event rate up 150kHz could be possible • Serial hit data for a fast track triggerM. Pernicka, Hephy, Vienna Manfred Pernicka, HEPHY Vienna

3. What exists and is working and what has to be done for final SVD-3 upgrade? • What could be included to reduce occupancy? • How could we get data for the trigger processor? • Who wants to contribute especially with M.C. simulation to qualify the occupancy reduction? • (Is a track trigger possible in a mixed (rz- and uv-) coordinate system?) • How can we correct the undershoot of the incoming signal after capacitive (AC) coupling? • Timing of the work, schedule after a definitive decision? • M. Pernicka Hephy,Vienna Manfred Pernicka, HEPHY Vienna

4. ADC module for the CMS-pixel system, Inputs have to be changed from optical to electrical signals on the mother board for BELLE. Clock, timing and trigger system needs modification and a part of the Altera has to be re-programmed. Opt. input for TTC VME 64x is possible Optical receiver has to be changed to RJ45 electr. Input connectors + ampl. TTCrx, needs new trigger timing system Bus P2 or P0 will be used 36 outputs with serial hit data (For trigger) S-link for 64 bit data 80 MHz transfer. simple handshake like old system but faster. Manfred Pernicka, HEPHY Vienna

5. Daughter board with 4 ADCs. Prototype tested and works. Final version ready for BELLE in 3 months, will be the same like that for Pixel readout system. Manfred Pernicka, HEPHY Vienna

6. Layout for the daughter board of the Altera EP1S20_F672 with EPROM and Voltage regulator (exists) No change Voltage regulator EPROM Each Connector 100 pins. We can use 360 for input/output. That limits the number of ADCs (one ADC 10 lines etc.) Every output is serially terminated on the mother board. Altera side view 14 mm Manfred Pernicka, HEPHY Vienna

7. Would be ready for BELLE: the complete event data block building can be used from the Pixel system (32 bit data bus sufficient). The APV25 data processor has to be programmed for BELLE. Manfred Pernicka, HEPHY Vienna

8. The delay for the ADC clock can be adjusted in steps of approximately 1.7 ns for optimum digitization point. Every input has its own data processor. The program to find hits in the data stream of the APV25 could be from the RAL CMS group or by us. How far we want to go in hardware (sparsification by Altera or by computer)? The hit data with position information will be ready at the same time for all inputs. The processing needs the same time span N*(128+K)*CLOCK_PERIOD as the readout (pipelined) -- no dead time or throttle. The limits are the APV25 and data transfer to the DAQ. Manfred Pernicka, HEPHY Vienna

9. Schematics of the ADC-Pixel with the possibility of single channel processing and output with data for trigger processor (largely exists) TTC input optical connection VME protocol Altera 4 times 10 bit data P 1 4 clocks with adjustable phase 9 lines with information for trigger proc. 4 ADC 12 input opt Transmit crate clock, control signals and event number Altera Daughter 9 inputs 9 data proc + FIFO’s P 0 64 (or 32 bit) bit data bus 40 MHz+4 control lines P 2 Data for trigger, serial TTC Altera daughter with final FIFO CMS Delayed clock and control sig.distributer, VME control Control bus 2 clocks phase shifted P 3 Fast data transfer to PCI Manfred Pernicka, HEPHY Vienna

10. Manfred Pernicka, HEPHY Vienna

11. Pulse scan (width = 2 clocks = 50 ns), time steps: clock/16 ~ 1.6 ns, error currently max +/- 0.4 ns (constant, not jitter), will be a lot better with the new lay out. Only one Altera for clock control for all inputs and delay steps. Manfred Pernicka, HEPHY Vienna

12. For test purposes Daughter board instead of optical link. Quick solution for test purposes. The current pixel module could be used already in “transparent” mode together with the sequencer in the BELLE system. Connector exists

13. How could we decrease the occupancy of the Si. strip detector ? The APV25 has the possibility to store 3 consecutive samples of a signal (multi-peak mode). When we use this possibility we get pulse height and peak time information (as long as the 3 analog data samples are around the peak). The second signal must be biggest. Manfred Pernicka, HEPHY Vienna

14. The shaping time is adjustable for the APV25

15. 12 time slices of a shaped input signal. 4 triggers with a time distance of 3 clocks S1 S2 S3 Manfred Pernicka, HEPHY Vienna

16. Time window where signal belongs to trigger Region where signal should be discarded, even though above threshold The shaping time only matters because of noise. But 25 ns would be to less in reality. The region must be larger than a clock width. (f.e. Ampl. Value reduced by a small factor) 25 ns S1 S2 S3 To be solved: How handle small signals? Threshold above which every signal would be stored using a discriminator. Manfred Pernicka, HEPHY Vienna

17. More possibilities for occupancy reduction without any loss of efficiency: send 2 consecutive triggers = 6 time samples, but only the first 4 are used Time window where signal belongs to trigger Region where signal should be discarded, even though above threshold The shaping time only matters because of noise. Now S2 or S3 must be greatest (and possibly other criteria). Acceptance window for hits will be wider than 25 ns > 25 ns S1 S2 S3 S4 Threshold above which every signal would be stored using a discriminator. Manfred Pernicka, HEPHY Vienna

18. With a short shaping time, we could maybe do even better occupancy reduction. The time between the real trigger information of the TOF, if exists (or other time references), and the clock synchronised trigger for the APV25 can be measured and transmitted to the FADC system. Region (S1~S3) <S2 reason noise and time jitter. For smaller signal the contribution is more great S1 S2 S3 region S1<=S3<S2 S1 S2 S3 region S3<=S1<S2 TOF (time) * xxx trig (x) for APV25 time between TOF and APV25Trig Manfred Pernicka, HEPHY Vienna Manfred Pernicka, Hephy , Vieanna

19. M. C. signal with noise Excepted as signal above threshold ~280 ns Selected with S1,S3<S2 Selected S1<S3<S2 and S3<S1<S2 <50ns ~25ns ~25ns Manfred Pernicka, HEPHY Vienna M. Friedl M.Pernicka, Hephy. Vienna

20. Input from the APV 25 after a trig. (1 or) 2 steps to calculate pedestal correction factor Subtracts threshold and checks if result > 0 Divide up in 3 time slices pipeline, data with position information Looks for data which belongs to the trigger. Use time information – real trigger/APV trigger. Transferred on the VME bus. Data rate reduction ! Time information real trigger/APV trigger input Serial trigger data output Try to increase the S/N using 3 time slices ? Manfred Pernicka, HEPHY Vienna Final event data: pulse height + position Hephy.vienna manfred Pernicka

21. A further possibility (???) to reduce the occupancy and select real data could be to use the cluster size. You know what you can expect for a certain angle. Cluster size increase in the u/v plane with absolute z Such a track will have a lot smaller cluster than a ‘’good’’ track Manfred Pernicka, HEPHY Vienna

22. Short summary of using 3 samples: Advantages 1. Data reduction and significant occupancy reduction. 2. A track trigger seems more realistic, could be possible? 3. Track finding should be easier. Disadvantages 1. Needs 3 times readout of APV25. When we use the first 128 data with reduced pulse height for a fast track trigger no time is lost. 2. Pile-up – 2 consecutive hits on one Si. strip – can cause a loss of hit information. Small signals are vulnerable by noise. Many open issues: How many steps for the threshold calculation? How far could the proposed occupancy reduction be in reality? Must be the final trigger output be synchronous or not to the real time of the trigger? Manfred Pernicka, HEPHY Vienna

23. AC coupling between REBO and FADC N*70*25 ns DAC starts to correct a second time Measured by the FADC DAC starts to correct the pedestal Measured by the FADC The remaining ‘’rest’’ will be done by the input procssor

24. ADC FPGA ALTERA En/disable time is known bus Enable when no data from APV25 Simple DAC

25. It is up to us: Once we can be demonstrate the feasibility of the suggested triggering scheme, we will gain a lot. Maybe pitch of Si. Det could be higher in the region of high eta (inclined tracks = less signal per strip)? Manfred Pernicka, HEPHY Vienna

26. Trigger proc. COPPER ??? Trigger lines from some ADC modules From every input a serial trigger data 36 (32) output 9 U V M E ? Hit Data for trig. proc buffer Event data block from all 36 (32) inputs 64 bit or 32 bit data S-link or ??? Manfred Pernicka, HEPHY Vienna

27. We want to investigate penguins, not be tricked by them... The End Manfred Pernicka, HEPHY Vienna