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This study investigates effective scheduling strategies for heterogeneous multi-core processors, focusing on static characteristics and parameters that influence performance. It contrasts heterogeneity-aware and oblivious schedulers, examining key metrics like execution migration, process differences, and signature generation via Euclidean distance. The research aims to enhance core selection and application steering, incorporating design considerations for job monitoring, scheduling policies, and testing frameworks to address challenges in workload diversity and dynamic input responsiveness.
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OS Driven Core Selection for HCMP Systems Anand Bhatia, RishkulKulkarni
Outcomes O Characterization – based on static parameters - Comparison – Heterogeneity aware vs oblivious scheduler O A functional core selector – OSDCS Module X Study of performance change O : Complete - : Partial X : Pending
Prior Work • Efficient program scheduling for heterogeneous multi-core processors – J. Chen, L.K. John • Static Characteristics • Euclidean distance based signature matching • HASS: A scheduler for Heterogeneous Multicore Systems - Shelepov, D., Fedorova et. al. • DVFS scaling • Process differences • A Unified View of Core Selection and Application Steering in Heterogeneous Chip Multiprocessors – SandeepNavada • Bottleneck counters • Execution migration
Phase 1 - Characterization • Signature Generation • Static Measurements • Dependence Distance (Issue Width) • Stack Distance (Cache Size) • Branch Variability (Branch Predictor Size) • Instructions Per Branch (Experimental) • Projection Functions • Core Exploration
Phase 1 - Results Representative Core Configs • Issue width | Dependence distance • BP Size | Branch variability • D$ Size | Stack Distance • AL Size | IPB IPC on chosen core configs • Independent runs • Useful to determine workload mix for scheduler
721sim 1 Phase 2 – OSDCS Module 721sim 2 Job Queue 721sim 3 Selector Issue Unit 721sim 4 Simulated Superscaler chip Interface Module User space Kernel space Selector LKM Fig. : Experimental setup used for ODCS Job Queue 721sim 1 Fake System call handler 721sim 2 721sim 3 721sim 4 Actual system call handler • Design Considerations • Design choices • Job Monitoring mechanisms Vs Fig : Booting OS on 721sim Cores
721sim 1 Phase 2 – OSDCS Module - 2 721sim 2 Job Queue 721sim 3 Issue Unit Selector 721sim 4 Simulated Superscaler chip Interface Module User space Kernel space Selector LKM Fig. : Experimental setup used for ODCS Design detailed. User selector Selector LKM Scheduling Policies.
Phase 2 - Policies Two different types: • Varying Schedule & Dispatch mechanisms • Greedy • Non work-conserving • Weights • Bias logically similar parameters heavily.
Testing Framework • Core Exploration • Signature generation using projection functions • Selecting cores • OSDCS Module • Virtual Machine with minimal Ubuntu • Run scripts
Limitations Insensitive to behavioral changes in workload phases Oblivious to dynamically changing inputs to workloads
Future Work Furthering OSDCS module to incorporate timing model Investigating specialized cores/accelerators. Devising projection functions for more parameters like IPB and LSQ sizing. Implement enhanced scheduling policies such as confidence based weighing.
Backup slide 1: Preliminary results. Caveat 1 : Limited job diversity, Reason: Many jobs assert out on core configurations chosen. Caveat 2 : Synthetic Batch Batch : 5 5 5 1 5 1 5 1 5 1 1 1 {All same , diverse, All same}
