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Chapter 8 Counters

Chapter 8 Counters. Combinational logic circuit: output only depends on the input. Sequential logic circuit: output not only depends on the input, but also depends on its original state. The analysis of synchronous sequential logic circuit. The process is as follows:

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Chapter 8 Counters

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  1. Chapter 8 Counters

  2. Combinational logic circuit: output only depends on the input. Sequential logic circuit: output not only depends on the input, but also depends on its original state.

  3. The analysis of synchronous sequential logic circuit The process is as follows: 1. Write driving equations of each flip-flop, that is write input logic expressions of each flip-flop. 2. Write state equations of each flip-flop. (substitute driving equations into the characteristic equations) 3. Write output equation according to logic circuit. 4. Drawing state transition table and state transition diagram. 5. Analyze logic function.

  4. example

  5. Q3 Q2 Q1 Q3* Q2* Q1* Y 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 State transition table—— method 1

  6. CLK Q3 Q2 Q1 Y 0 0 0 0 0 1 0 0 1 0 2 0 1 0 0 3 0 1 1 0 1 0 0 0 4 1 0 1 5 0 6 1 1 0 1 7 0 0 0 0 0 1 1 1 1 1 0 0 0 0 State transition table——method 2

  7. State transition diagram

  8. Sequential diagram

  9. Synchronous decimal addition counter

  10. Function table

  11. Two methods to design counter（a） Asynchronous reset（b）Synchronous load

  12. Senary counter Output carry (a) Asynchronous reset

  13. State transition diagram

  14. output carry （b）Synchronous load load 0000

  15. Output carry load 1001

  16. State transition diagram

  17. 74161 Synchronous hexadecimal addition counter

  18. & Q0 Q1 Q2 Q3 1 1 EP C ET CP CP 1 D0 D1 D2 D3 74161 LD RD Design a septenary counter ---------- asynchronous reset

  19. 0000 0001 0010 0011 0100 1111 0101 1110 0110 1101 0111 1100 1011 1010 1001 1000

  20. & Q0 Q1 Q2 Q3 1 EP C ET 1 74161 CP CP D0 D1 D2 D3 LD RD Design a septenary counter ---------- synchronous load

  21. 0000 0001 0010 0011 0100 1111 0101 1110 0110 1101 0111 1100 1011 1010 1001 1000

  22. Q0 Q1 Q2 Q3 1 EP C ET 1 CP CP D0 D1 D2 D3 1 0 1 0 LD RD Determine the number of the counter Senary counter & 74161

  23. Cascaded counters Counters can be connected in cascade to achieve higher-modulus operation. Cascading means that the last-stage output of one counter drives the input of the next counter.

  24. Asynchronous 二－五－十counter (74LS290)

  25. Parallel carry method

  26. series carry method

  27. Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 EP C 1 EP C ET 74161(1) 74161(2) ET CP CP D0 D1 D2 D3 1 D0 D1 D2 D3 1 CP RD LD LD RD

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