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Counters

This guide explores asynchronous (ripple) counters, which are circuits that cycle through defined states without a common clock pulse. We discuss their characteristics, including how the output of one flip-flop connects to the clock of another, thus creating ripple effects. Key examples, like 2-bit, 3-bit, and 4-bit counters, illustrate their functioning. While asynchronous counters are simpler, they have notable propagation delays that can affect performance. Learn about the design of decade (BCD) counters and the distinction between up and down counting.

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Counters

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  1. Counters

  2. Introduction: Counters • Counters are circuits that cycle through a specified number of states. • Two types of counters: • synchronous (parallel) counters • asynchronous (ripple) counters • Ripple counters allow some flip-flop outputs to be used as a source of clock for other flip-flops. • Synchronous counters apply the same clock to all flip-flops. Introduction: Counters

  3. Asynchronous (Ripple) Counters • Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse. • Also known as ripple counters, as the input clock pulse “ripples” through the counter – cumulative delay is a drawback. • n flip-flops  a MOD (modulus) 2n counter. (Note: A MOD-x counter cycles through x states.) • Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider. Asynchronous (Ripple) Counters

  4. J J HIGH K K Q0 Q1 C C CLK Q0 FF1 FF0 CLK 1 2 3 4 Q0 Q0 0 1 0 1 0 Q1 0 0 1 1 0 Asynchronous (Ripple) Counters • Example: 2-bit ripple binary counter. • Output of one flip-flop is connected to the clock input of the next more-significant flip-flop. Timing diagram 00  01  10  11  00 ... Asynchronous (Ripple) Counters

  5. HIGH J J J Q0 Q1 Q2 CLK C C C Q0 Q1 K K K FF0 FF2 FF1 CLK 1 2 3 4 5 6 7 8 Q0 0 1 0 1 0 1 0 1 0 Q1 0 0 1 1 0 0 1 1 0 Q2 0 0 0 0 1 1 1 1 0 Recycles back to 0 Asynchronous (Ripple) Counters • Example: 3-bit ripple binary counter. Asynchronous (Ripple) Counters

  6. CLK 1 2 3 4 Q0 Q1 Q2 tPHL (CLK to Q0) tPHL (CLK to Q0) tPHL (Q0 toQ1) tPLH (Q0 toQ1) tPLH (CLK to Q0) tPLH (Q1 toQ2) Asynchronous (Ripple) Counters • Propagation delays in an asynchronous (ripple-clocked) binary counter. • If the accumulated delay is greater than the clock pulse, some counter states may be misrepresented! Asynchronous (Ripple) Counters

  7. J J J J HIGH Q0 Q1 Q2 Q3 CLK C C C C K K K K FF0 FF1 FF2 FF3 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Q0 Q1 Q2 Q3 Asynchronous (Ripple) Counters • Example: 4-bit ripple binary counter (negative-edge triggered). Asynchronous (Ripple) Counters

  8. C B A Q Q Q J J J CLK CLK CLK All J, K inputs are 1 (HIGH). K K K Q Q Q CLR CLR CLR B C Asyn. Counters with MOD no. < 2n • States may be skipped resulting in a truncated sequence. • Technique: force counter to recycle before going through all of the states in the binary sequence. • Example: Given the following circuit, determine the counting sequence (and hence the modulus no.) Asynchronous Counters with MOD number < 2^n

  9. C B A All J, K inputs are 1 (HIGH). B C 1 2 3 4 5 6 7 8 9 10 11 12 MOD-6 counter produced by clearing (a MOD-8 binary counter) when count of six (110) occurs. Clock Q Q Q J J J A CLK CLK CLK K K K Q Q Q B CLR CLR CLR C NAND Output 1 0 Asyn. Counters with MOD no. < 2n • Example (cont’d): Asynchronous Counters with MOD number < 2^n

  10. 1 2 3 4 5 6 7 8 9 10 11 12 Clock A B C NAND Output 1 0 111 Temporary state 001 000 010 101 011 100 110 Asyn. Counters with MOD no. < 2n • Example (cont’d): Counting sequence of circuit (in CBA order). 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 Counter is a MOD-6 counter. Asynchronous Counters with MOD number < 2^n

  11. F E D C B A Q Q Q Q Q Q J J J J J J C D EF Q Q Q Q Q Q K K K K K K All J = K = 1. CLR CLR CLR CLR CLR CLR Asyn. Counters with MOD no. < 2n • Exercise: How to construct an asynchronous MOD-5 counter? MOD-7 counter? MOD-12 counter? • Question: The following is a MOD-? counter? Asynchronous Counters with MOD number < 2^n

  12. (A.C)' HIGH D C B A CLK J J J J Q Q Q Q C C C C K K K K CLR CLR CLR CLR Asyn. Counters with MOD no. < 2n • Decade counters (or BCD counters) are counters with 10 states (modulus-10) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.). • Design an asynchronous decade counter. Asynchronous Counters with MOD number < 2^n

  13. HIGH D C B A (A.C)' J Q J Q J Q J Q C C C C CLK K K K K CLR CLR CLR CLR 1 2 3 4 5 6 7 8 9 10 11 Clock D 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 C B A NAND output Asyn. Counters with MOD no. < 2n • Asynchronous decade/BCD counter (cont’d). 0 0 0 0 Asynchronous Counters with MOD number < 2^n

  14. J J J J J J K K K K K K 1 Q2 Q0 Q1 Q Q Q Q Q Q Q C C CLK C Q' Q' Q' Q' Q' Q' Q' 1 Q2 Q0 Q1 Q C C CLK C Q' Asynchronous Down Counters • So far we are dealing with up counters. Down counters, on the other hand, count downward from a maximum value to zero, and repeat. • Example: A 3-bit binary (MOD-23) down counter. 3-bit binary up counter 3-bit binary down counter Asynchronous Down Counters

  15. J J J K K K CLK 1 Q Q Q 2 3 4 5 6 7 8 Q' Q' Q' Q0 0 1 0 1 0 1 0 1 0 101 011 010 110 100 001 000 111 Q1 0 1 1 0 0 1 1 0 0 1 Q2 Q2 Q0 Q1 0 1 1 1 1 0 0 0 0 Q C C CLK C Q' Asynchronous Down Counters • Example: A 3-bit binary (MOD-8) down counter. Asynchronous Down Counters

  16. J J J J J K K K K K Q Q Q Q Q Q' Q' Q' Q' Q' Q0 Q1 Q2 Q3 Q4 Q Q C C C CLK C C Q' Q' Modulus-4 counter Modulus-8 counter Cascading Asynchronous Counters • Larger asynchronous (ripple) counter can be constructed by cascading smaller ripple counters. • Connect last-stage output of one counter to the clock input of next counter so as to achieve higher-modulus operation. • Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter. Cascading Asynchronous Counters

  17. A0A1A2 A3A4A5 Count pulse 3-bit binary counter 3-bit binary counter Cascading Asynchronous Counters • Example: A 6-bit binary counter (counts from 0 to 63) constructed from two 3-bit counters. Cascading Asynchronous Counters

  18. freq/10 1 CTEN CTEN freq/100 Decade counter Decade counter TC TC CLK C C Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 freq Cascading Asynchronous Counters • If counter is a not a binary counter, requires additional output. • Example: A modulus-100 counter using two decade counters. TC = 1 when counter recycles to 0000 Cascading Asynchronous Counters

  19. 01 00 10 11 Synchronous (Parallel) Counters • Synchronous (parallel) counters: the flip-flops are clocked at the same time by a common clock pulse. • We can design these counters using the sequential logic design process (covered in Lecture #12). • Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs). Synchronous (Parallel) Counters

  20. J J K K Q Q Q' Q' 1 A0 A1 Q C C Q' CLK Synchronous (Parallel) Counters • Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs). TA1 = A0 TA0 = 1 Synchronous (Parallel) Counters

  21. A1 1 1 1 1 A2 1 1 1 1 A1 A0 1 A1 A2 1 1 1 A0 A2 1 1 A0 Synchronous (Parallel) Counters • Example: 3-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J, K inputs). TA2 = A1.A0 TA1 = A0 TA0 = 1 Synchronous (Parallel) Counters

  22. A2 A1 A0 Q Q Q J J J K K K CP 1 Synchronous (Parallel) Counters • Example: 3-bit synchronous binary counter (cont’d). TA2 = A1.A0TA1 = A0TA0 = 1 Synchronous (Parallel) Counters

  23. Synchronous (Parallel) Counters • Note that in a binary counter, the nth bit (shown underlined) is always complemented whenever 011…11 100…00 or 111…11 000…00 • Hence, Xn is complemented whenever Xn-1Xn-2 ... X1X0 = 11…11. • As a result, if T flip-flops are used, then TXn = Xn-1 . Xn-2 . ... . X1 .X0 Synchronous (Parallel) Counters

  24. J J K K A1.A0 1 A2.A1.A0 Q Q Q Q A0 A1 A2 A3 J J Q Q' Q' Q' Q' C C C C Q' K K CLK Synchronous (Parallel) Counters • Example: 4-bit synchronous binary counter. TA3 = A2 . A1. A0 TA2 = A1. A0 TA1 = A0 TA0 = 1 Synchronous (Parallel) Counters

  25. Synchronous (Parallel) Counters • Example: Synchronous decade/BCD counter. T0 = 1 T1 = Q3'.Q0 T2 = Q1.Q0 T3 = Q2.Q1.Q0 + Q3.Q0 Synchronous (Parallel) Counters

  26. T T T T Q Q Q Q Q' Q' Q' Q' Q0 Q1 Q2 Q3 1 Q Q Q Q C C C C Q' Q' Q' Q' CLK Synchronous (Parallel) Counters • Example: Synchronous decade/BCD counter (cont’d). T0 = 1 T1 = Q3'.Q0 T2 = Q1.Q0 T3 = Q2.Q1.Q0 + Q3.Q0 Synchronous (Parallel) Counters

  27. Up/Down Synchronous Counters • Up/down synchronous counter: a bidirectional counter that is capable of counting either up or down. • An input (control) line Up/Down (or simply Up) specifies the direction of counting. • Up/Down = 1  Count upward • Up/Down = 0  Count downward Up/Down Synchronous Counters

  28. Up/Down Synchronous Counters • Example: A 3-bit up/down synchronous binary counter. TQ0 = 1 TQ1 = (Q0.Up) + (Q0'.Up' ) TQ2 = ( Q0.Q1.Up )+ (Q0'. Q1'. Up' ) Up counter TQ0 = 1 TQ1 = Q0 TQ2 = Q0.Q1 Down counter TQ0 = 1 TQ1 = Q0’ TQ2 = Q0’.Q1’ Up/Down Synchronous Counters

  29. T T T Q Q Q Q0 Q1 Q' Q' Q' Q2 1 Up Q Q Q C C C Q' Q' Q' CLK Up/Down Synchronous Counters TQ0 = 1 TQ1 = (Q0.Up) + (Q0'.Up' ) TQ2 = ( Q0.Q1.Up )+ (Q0'. Q1'. Up' ) • Example: A 3-bit up/down synchronous binary counter (cont’d). Up/Down Synchronous Counters

  30. 000 100 001 101 111 110 011 010 Designing Synchronous Counters • Covered in Lecture #12. • Example: A 3-bit Gray code counter (using JK flip-flops). Designing Synchronous Counters

  31. Q1Q0 Q1Q0 Q1Q0 Q2 Q2 Q2 00 01 11 10 00 01 11 10 00 01 11 10 0 1 1 0 1 1 X X 0 1 1 X X X X X X X X X X 1 JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = Q2.Q1 + Q2'.Q1' = (Q2Q1)' Q1Q0 Q1Q0 Q1Q0 Q2 Q2 00 01 11 10 00 01 11 10 Q2 00 01 11 10 0 1 X X 0 1 X 1 X 0 1 X X X X X X 1 X 1 X 1 KQ1 = Q2.Q0 KQ0 = Q2.Q1' + Q2'.Q1 = Q2Q1 KQ2 = Q1'.Q0' Designing Synchronous Counters • 3-bit Gray code counter: flip-flop inputs. Designing Synchronous Counters

  32. Q0 Q1 Q2 J J J Q Q Q C C C Q1' Q2' K K K Q' Q' Q' Q0' CLK Designing Synchronous Counters • 3-bit Gray code counter: logic diagram. JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = (Q2Q1)' KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2Q1 Designing Synchronous Counters

  33. Shift Register Counters • Ring Counters • A ring counter is basically a circulating shift register in which the output of the most significant stage is fed back to the input of the least significant stage.  The following is a 4-bit ring counter constructed from D flip-flops.  The output of each stage is shifted into the next stage on the positive edge of a clock pulse.  If the CLEAR signal is high, all the flip-flops except the first one FF0 are reset to 0.  FF0 is preset to 1 instead.

  34. Shift Register Counters • Since the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter.  Only 4 of the maximum 16 states are used, making ring counters very inefficient in terms of state usage.  But the major advantage of a ring counter over a binary counter is that it is self-decoding.  No extra decoding circuit is needed to determine what state the counter is in.

  35. Shift Register Counters • Johnson Counters

  36. Shift Register Counters • Again, the apparent disadvantage of this counter is that the maximum available states are not fully utilized.  Only eight of the sixteen states are being used. • Beware that for both the Ring and the Johnson counter must initially be forced into a valid state in the count sequence because they operate on a subset of the available number of states.  Otherwise, the ideal sequence will not be followed.

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