Overview of Trigger Board CDR by Matthew Warren - University College London
This document presents an overview of the Trigger Board CDR designed by Matthew Warren at University College London on October 11, 2002. The board features a 6U slave module with a 16-bit data bus, inclusive of flexible I/O, support for incoming triggers, and potential usage in alien crates. Key components include a large CPLD, multiple delay units, and comprehensive signal management with LVDS connections. The design focuses on configurability, efficient signal processing, and robust operation under specified conditions, with insightful details on firmware and system architecture.
Overview of Trigger Board CDR by Matthew Warren - University College London
E N D
Presentation Transcript
Trigger Board CDR Matthew Warren University College London 11 October 2002 Matthew Warren - Trigger Board CDR
Overview VME Module - 6U, Slave - 16 bit Data Bus (D32 okay, but only lower 16 bits data) All requirements not known - Incoming trigger unspecified - Use in ‘alien’ crates possible - Trigger destinations unspecified (HCAL ReadOut design?) = Must have flexible I/O = Able to operate at 5V = Configurable operation - CPLD ideal Matthew Warren - Trigger Board CDR
On the PCB Front-panel and Back-plane NIM/LVDS - see next slide Single, large CPLD 2 Delay-units - 64 2-5ns steps each - detect excessive Activity 50MHz Local Clock Base Address select hex-switches Super-dumb Mode jumpers - bypasses CPLD entirely Power pin select jumpers - including JAux option 8 pin Debug header for ‘scope or logic analyser Buffers for all VME signals Matthew Warren - Trigger Board CDR
External I/O Front-panel NIM: 10 Inputs, 10 Outputs - Double height LEMO 00 connectors - Each signal connected to CPLD LVDS: 10x4 Fan-out - 4 IDC 20-way connectors - 10 Individual CPLD signals - Fanned-out with hardware - Custom PSU powered (only works is our crate) Back-plane LVDS: 4 Outputs - uses custom J2 pins - custom PSU powered Matthew Warren - Trigger Board CDR
Generic Operation NIM - All Inputs have Outputs In-Modify-Out design Allows master-slave configuration of multiple Trigger Boards CPLD BSigOut SigIn SigOut LSigOut enSigIn VSig enSigOut VME Matthew Warren - Trigger Board CDR
Firmware (or Why Use a CPLD...) VME Interface (asynchronous) VME generated Triggers etc. Status register Test registers (and stand-alone testability) Signal enables (Inputs and Outputs) Generate stand-alone 12.5MHz read-out clock Long Delays (20ns/80ns steps) Trigger-Veto-Abort cycle state-machine Activity Auto-Abort (using delay-units) Counters (Trigger number etc.) Timers Matthew Warren - Trigger Board CDR
CPLD/Pins Requirements: - 167 pins + 20% margin = ~200 pins - 7ns required for 50Mhz clock - 5V Component simplifies design - Need ample logic Quickest design route – Xilinx Spartan II - Schematics for other components - Firmware too Matthew Warren - Trigger Board CDR
Summary • Missing info on input/output and specific functions? • Goal is to have room for whatever is asked of us: • - Enough I/O • - Enough Pins • Enough Support Hardware Matthew Warren - Trigger Board CDR
